Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Jan Kok

John G McBride

In addition to the normal circuitry which provides the normal computation, a microprocessor is provided with one or more additional but simplified central processing units which allows additional threads of execution to occur at a slower rate. The purpose of the secondary threads is to prefetch data from external storage to main memory or from main memory to cache in order to minimize waiting by the primary thread.

Multithreaded microprocessor with asymmetrical central processing units

An electrical rules checker system and method are provided to identify tri-state logic from a netlist. In accordance with one aspect of the invention, a method identifies tri-state logic from a netlist by selecting a circuit configuration to be identified, and then identifying any of the circuit configurations at the node, and identifyng any probable circuit configurations at the node. In accordance with another aspect of the invention, a system is provided for identifying tri-state logic connected to a selected node of an integrated circuit. The system operates by evaluating a netlist at the node, and further includes a code segment for selecting a circuit configuration to be identified, a second code segment for identify any of the selected circuit configurations a given node in a netlist, and a third code segment configured to identify any probable circuit configurations at the node in a netlist.

Electrical rules checker system and method using tri-state logic for electrical rule checks

An electrical rules checker system and method are provided to report any errors discovered during appraisal of an element at a node in a netlist. In accordance with one aspect of the invention, a method selects a circuit configuration to be identified. Next, identify any element at a node, equal to or virtually equal to said circuit configuration. Then, the element equal to and virtually equal to said circuit configuration is appraised. Finally, any error discovered during appraisal of the element at the node is reported. hi accordance with another aspect of the invention, a system is provided for appraising tri-state logic connected to a selected node of an integrated circuit. The system operates by a code segment selecting a circuit configuration to be identified. A second code segment identifies any element at a node, equal to said circuit configuration, and a third code segment identifies any element at the node virtually equal to said circuit configuration. A fourth code segment appraises the element equal to and virtually equal to the circuit configuration, and a fifth code segment reports any error discovered during appraisal of the element at the node.

Electrical rules checker system and method for reporting problems with tri-state logic in electrical rules checking

An electrical rules checker system and method are provided to appraise tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist. In accordance with one aspect of the invention, the method selects a circuit configuration to be identified. Next, the method identifies any of the circuit configurations at the node, and identifies any probable circuit configurations at the node. Then the method appraises the circuit configurations and the probable circuit configurations. In accordance with another aspect of the invention, a system is provided for appraising tri-state logic connected to a selected node of an integrated circuit. The system operates by evaluating a netlist at the node, and further includes a code segment for selecting a circuit configuration to be identified, a second code segment for identify any of the selected circuit configurations a given node in a netlist, and a third code segment configured to identify any probable circuit configurations at the node in a netlist. A fourth code segment appraises the identified circuit configurations and probable circuit configurations.

Electrical rules checker system and method providing quality assurance of tri-state logic

The present invention is directed to a system and method for identifying multiplexers from a netlist. In accordance with one aspect of the invention, a method identifies multiplexers from a netlist by identifying both an input node and an output node of a pass gate. The method then identifies all FETs that are channel connected to the output node, and evaluates all FETs that are identified as being channel connected to the output node, to determine whether they are pass FETs. Finally, the method determines whether at least one of the identified pass FETs has an output that is the same node as the output node and an input that is not the same node as the input node. In accordance with another aspect of the invention, the method identifies a node in the netlist that is an output node of a first pass FET and identifies at least one other pass FET that has an output that is the same node as the output node. Finally, the method evaluates the at least one other pass FET to determine whether an input of that other at least one other pass FET is not the same node as an input node of the first pass FET.

System and method for detecting multiplexers in a circuit design

A method and apparatus for generating a database to be utilized by a rules checker for evaluating the quality of a particular design, such as, for example, an integrated circuit design. The design to be evaluated comprises a plurality of elements coupled together by at least one node. The apparatus of the present invention comprises a computer running a database generation program which receives, as its input to the database generation program, information relating to characteristics of the elements and nodes. The database generation program utilizes the input to produce a data structure for each of the elements and nodes. These data structures comprise the database which can be utilized by the rules checker to evaluate the quality of the design. In accordance with the preferred embodiment of the present invention, the input to the database generation program corresponds to the output of a timing analyzer program which is being executed by the computer. The design is an electrical circuit design and the output of the static timing analyzer program includes statistical and other information relating to the elements and nodes in the electrical circuit design. This information is then utilized by the database generation program to generate the data structures for the elements and nodes. These data structures comprise the database which is utilized by the rules checker program to evaluate the quality of the circuit design.

Method and apparatus for generating a database which is used for determining the design quality of network nodes

To achieve the advantages and novel features, the present invention is generally directed to a system and method for identifying pass FETs from a netlist. In accordance with one aspect of the invention, a method identifies pass FETs from a netlist by identifying complementary pass FET circuit configurations at each node, identifying RAM pass FET circuit configurations at the node, and identifying single pass FET circuit configurations at the node. In accordance with another aspect of the invention, a system is provided for identifying pass FETs connected to a selected node of an integrated circuit. The system operates by evaluating a netlist at the node, and further includes a code segment for identifying complementary pass FET circuit configurations at the node, a code segment for identifying RAM pass FET circuit configurations at the node, and a code segment for identifying single pass FET circuit configurations at the node.

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Fort Collins, CO, United States of America

Jan Kok