Greenpeak Technologies B.v.

Trident Microsystems (far East) Ltd.

Jan Hendrik Haanstra

Edwin Jan Schapendonk

Hans Van Driest

Anton Willem Roodnat

Richard Jan Engel Jansen

Willebrordus Gerardus Traa

Disclosed is a transceiver including a sub-sampling based frequency synthesizer with a sampling frequency f, configured to generate M different output signalsfor use as a carrier signal for transmission and/or a signal with a channel frequency for reception. M is an integer greater than 4, each output signal has a corresponding predefined frequency. The predefined frequencies are within a frequency band with a predefined bandwidth CFR. CFR is greater than f. The frequency synthesizer includes a frequency shift unit configured for shifting a version of the output signal over a predefined frequency shift fto obtain a frequency shifted signal which is supplied to a sampling unit of the sub-sampling based frequency synthesizer, wherein &#x2212;f/2&#x2266;f&#x2266;+f/2. The frequency shift unit is configured to use for the generation of each of the N different output signals a corresponding predefined frequency shift f.

Transceiver with sub-sampling based frequency synthesizer

Biasing circuit for providing a supply voltage (Vdd) for an inverter based circuit. The biasing circuit is provided on a same die as the inverter based circuit, and includes a first shorted inverter circuit (T, T) and a second shorted inverter circuit (T, T). The first shorted inverter circuit (T, T) is connected in parallel to a series configuration of the second shorted inverter circuit (T, T) and a reference impedance (R). The first shorted inverter circuit (T, T) and second shorted inverter circuit (T, T) have different transistor geometries. A control circuit (T-T) is connected to the first shorted inverter circuit (T, T) and the second shorted inverter circuit (T, T), and supplied with a main supply voltage (Vdd). The control circuit (T-T) is arranged such that an equal current flows through the first shorted inverter circuit (T, T) and second shorted inverter circuit (T, T).

Biasing in CMOS inverter

In a signal processor, a sampling arrangement (SH, S, SH, ADC) samples at least a first signal (YA) and a second signal (UA, VA) so as to obtain sampled first signal (YD) and a sampled second signal (UD, VD), respectively. A folding compensator (LPF, LPF, LPF, SUB, SUB, MUX) compensates for a folding component in the sampled first signal (YD) on the basis of a spectral portion of the sampled second signal (UD, VD) that is substantially free of components that originate from the second signal (UA, VA).

Growing community of inventors

Nijmegen, Netherlands

Jan Hendrik Haanstra