Nxp B.v.

Jan Gulpen

Tonny Kamphuis

Leo Van Gemert

Leonardus Antonius Elisabeth Van Gemert

Pieter Hochstenbach

Eric Van Grunsven

Marc De Samber

Antonius Hendrikus Jozef Kamphuis

Jan Willem Bergman

Jetse De Witte

Roelf Groenhuis

A method of making a plurality of packaged semiconductor devices. The method includes providing a carrier blank having a die receiving surface and an underside. The method also includes mounting a plurality of semiconductor dies on the die receiving surface, wherein the dies extend to a first height above the die receiving surface. The method further includes depositing an encapsulant on the die receiving surface, wherein an upper surface of the encapsulant is located above said first height. The method also includes singulating to form the plurality of packaged semiconductor devices by sawing into the underside, through the carrier blank and partially through the encapsulant to a depth intermediate the first height and the upper surface, wherein said sawing separates the carrier blank into a plurality of carriers, and removing encapsulant from the upper surface of the encapsulant at least until said saw depth is reached.

Method of making a plurality of packaged semiconductor devices

This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.

Wafer level chip scale semiconductor package

Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.

Shielded QFN package and method of making

Embodiments of a packaged semiconductor device with no leads are disclosed. One embodiment includes a semiconductor chip and a no leads package structure defining a boundary and having a bottom surface and includes three or more pads exposed at the bottom surface of the package structure. Each of the pads is located in a single inline row.

Single inline no-lead semiconductor package

A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.

Growing community of inventors

Nijmegen, Netherlands

Jan Gulpen