Telefonaktiebolaget Lm Ericsson (Publ)

Infineon Technologies Ag

Signal Processing Devices Sweden Ab

Ivp Integrated Vision Products Ab Teknikringen

Jan-Erik Eklund

Mikael Rudberg

Michael Lewis

Jonas Nilsson

Ragnar Arvidsson

Frida Eng

Linnéa Rosenbaum

Mattias Duppils

Anders Edman

A processing device () for a radio-receiver circuit () is disclosed. The radio-receiver circuit comprises an input terminal () for receiving an analog input signal, circuitry () for generating a compensated analog input signal by subtracting an analog compensation signal from the analog input signal, an analog-to-digital converter () arranged to receive the compensated analog input signal on an input terminal of the analog-to-digital converter (), and circuitry () for to generating the analog compensation signal based on a digital compensation signal. The processing device () comprises: an input terminal () for receiving an output signal of the analog-to-digital converter (); and an output terminal () for supplying the digital compensation signal. The processing device () is adapted to: generate an estimate of a blocking signal component in the analog input signal of the radio receiver circuit () based on the output signal of the analog-to-digital converter (); and generate the digital compensation signal based on said estimate such that said blocking signal component is at least partially cancelled in the compensated analog input signal. Embodiments of radio receiver circuit, integrated circuit, electronic apparatus, method, computer program, computer readable medium and hardware-description entity are also disclosed.

Device and method for blocking-signal reduction

A device () for generating a digital output signal by digitizing an analog input signal is disclosed. The device () comprises a first signal path comprising a first ADC () arranged to convert a first component of the analog input signal, residing in a first frequency band (), to a first digital signal, and a second signal path comprising a second ADC () arranged to convert a second component of the analog input signal, residing in a second frequency band (), to a second digital signal. The first and the second frequency band () overlap, such that there is a common frequency sub band (), which is comprised in both the first and the second frequency band (). The device () comprises a combination unit (). The combination unit () is adapted to determine, based on signal content of the first and second digital signal in the common frequency sub band (), at least one parameter indicating a mismatch between the first and the second signal path in the common frequency sub band (). Furthermore, the combination unit () is adapted to generate a first compensated digital signal and a second compensated digital for compensating the mismatch between the first and the second signal path in the common frequency sub band (). Moreover, the combination unit () is adapted to combine the first compensated digital signal and the second compensated digital signal for generating the digital output signal. Corresponding methods are also disclosed.

Device and method for digitizing a signal

Implementations related to media playback and storage devices are presented herein.

Device playback using radio transmission

Methods, articles of manufacture and systems for the correction of static mismatch errors in D/A converters, where an input word, being the digital representation of an analog input signal, is divided into one most significant part, msb-word, and one least significant part, lsb-word, where msb-word is represented by msb-bits and lsb-word is represented by lsb-bits. Correction is performed by setting the effective weight of the least significant msb-bit to be less than the total sum of all lsb-bits, implementing a first look up table, LUT, containing the most significant part of the error, so that a corrected msb-word, c-msb-word, would be equal to the msb-word plus a value in LUTrepresenting the msb-word, and implementing a second look up table, LUT, containing the least significant part of the error, so that a first corrected output, c1-output, would be equal to c-msb-word plus a value in LUTrepresenting the c-msb-word added to the lsb-word.

Correction of static mismatch errors in a D/A converter

A switched-capacitor circuit includes a plurality of sequentially-operated switched-capacitors A first capacitor is arranged to be coupled and thereafter uncoupled to an input signal during a first time period. Thereby the first capacitor is charged to an input value in dependence on the input signal. A second capacitor is arranged to be coupled and thereafter uncoupled to the first capacitor during a second time period for charge distribution between the second and first capacitor. Pairwise charge distribution is possibly done with further sequentially-operated switched capacitors. A final capacitor is arranged to be coupled and thereafter uncoupled to a previous capacitor during the final time period for charge distribution between the final and the previous capacitor. The switched-capacitor circuit further includes selectively coupling the first and the second sequentially-operated switched-capacitors to an output circuit thereby enabling a desired weighting of the input signal to be attained.

Switched capacitors

The present invention relates to a method of offset compensating a parallel analogue-digital converter that includes at least two channels ( ), where the analogue to digital conversion takes place simultaneously in the various channels but offset relative to respective channels. An analogue input signal ( ) to the analogue-digital converter is multiplied by &plus;1 or by &minus;1 in accordance with an arbitrary pattern and the output signal from the analogue-digital converter is multiplied by &plus;1 or by &minus;1 in accordance with the same arbitrary pattern as that by which the input signal was multiplied. The invention also includes a parallel analogue-digital converter for carrying out the method.

Offset compensation in parallel analogue-digital converters

The present invention relates to a device for the input and processing of information comprising sensor elements arranged in matrix form, which are integrally formed on a substrate. Each sensor element comprises output electronics (,) and at least one photovoltaic cell (PD), which is adapted to convert an optical signal incident upon the photovoltaic cell to an electrical signal. The device according to the invention is characterized in that each sensor element is adapted to perform compensation of an offset error in the output electronics (,) forming part of the sensor element and that each sensor element is adapted to perform the said offset compensation independently of the other sensor elements in the device.

Sensor element array for reading and processing image information

An analog-to-digital converter (ADC) has a histogram based correction of static errors. In a control and calculating unit (,) of the converter thus the counts of uncorrected digital output codes are stored in a memory (,). From the stored counts a model distribution is determined in a calculation unit, e.g. by estimating an expected gaussian distribution. The model distribution is compared to the measured counts and relative errors of the counts are calculated, the relative errors indicating errors in coarse reference levels. The errors are used for calculating correction terms (L(A)) stored in a correction table (,). The correction terms are used by an output calculating unit (,&prime;) to calculate corrected, more accurate output codes. For a parallel ADC device having several cells, the histograms in the cells can be used to correct for gain and offset errors. Also, the histogram can be used in a built-in self test. A reference level generator can be only partially common to the cells in a parallel ADC providing accurate coarse levels without cross-talk.

Correction static errors in a/d-converter

A process and device for providing an analog-to-digital conversion employing a successive approximation principle is provided. The search interval from a value X to a Value Y, which represents the value interval in which an unknown analog signal is to be converted to a digital signal value, is divided into a number of smaller search intervals, being divided into different area for employing a successive approximation process to iterate to the desired digital signal value. Further, reference levels are defined for each search interval to coincide with at least one other reference level, where coinciding reference level belongs to two search intervals formed by areas in a nearest larger search interval.

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Linköping, Sweden

Jan-Erik Eklund