Imec Vzw

Imec

Vrije Universiteit Brussel

Renesas Electronics Corporation

Interuniversitair Microelektronica Centrum (imec)

Sony Semiconductor Solutions Corporation

Stichting Imec Nederland

Jan Craninckx

Ewout Martens

Benjamin Hershberg

Nereo Markulic

Bob Verbruggen

Pierre Wambacq

Mark Ingels

Kazuaki Deguchi

Davide Dermit

Jorge Luis Lagos Benites

Takaya Yamamoto

Julien Ryckaert

Jonathan Borremans

Keigo Bunsen

Yao-Hong Liu

Maarten De Bock

Tomohiro Sano

Davide Guermandi

Masao Iriguchi

Khaled Khalaf

Giuseppe Gramegna

Barend Wilhelmus Marinus Van Liempd

Vito Giannini

Yang Zhang

Pedro Emiliano Paro Filho

Miguel Glassee

Johan Nguyen

Dries Hauspie

Holger Kuhnert

Sehoon Park

Pedro Paro Filho

Mark Maria Albert Ingels

Shun Nagata

Guiseppe Gramegna

A slope analog-to-digital converter, ADC, for converting an analog input signal to a digital representation, said slope ADC comprising: a comparator configured to compare two input signals, wherein a sampled value of the analog input signal and a slope signal are used in forming the two input signals; a memory element, which is configured to receive a trigger signal based on the comparator identifying a change in which of the two input signals is higher, and a counter signal, wherein a value of the counter signal when the trigger signal is received provides the digital representation of the sampled value of the analog input signal; wherein the slope signal and the counter signal have a nonlinear relationship, wherein the nonlinear relationship is adapted to improve linearity of a transfer function of the slope ADC for converting the analog input signal to the digital representation.

Slope analog-to-digital converter, a system and a method for converting an analog input signal to a digital representation

There is provided an analog-to-digital converter circuit including: a first converter circuit generating a first digital code by performing analog-to-digital conversion on the basis of an input voltage; a second converter circuit generating a second digital code by performing, on the basis of the input voltage and the first digital code, analog-to-digital conversion over a voltage range wider than that of a least significant bit of the first converter circuit; an error detector detecting a conversion error of the analog-to-digital conversion on the basis of the first and second digital codes, thereby generating error data indicating a bit having a conversion error and the kind of the conversion error; and a calibration circuit estimating an error factor on the basis of the first and second digital codes and the error data, and performing calibration of a circuit relevant to the estimated error factor on the basis of an estimation result.

Analog-to-digital converter circuit

A phased array transceiver element comprises a local oscillator stage for generating beamformed in-phase and quadrature local oscillator signals, the local oscillator stage comprising a phase shifter connectable to a reference frequency source and applying a first phase shift; a primary frequency multiplier input from the phase shifter and applying a primary frequency multiplication factor; a phase-splitting arrangement input from the primary frequency multiplier and having a first output and a second output, the phase-splitting arrangement applying a second phase shift at the first output and a third phase shift at the second output; a first secondary frequency multiplier input from the first output of the phase-splitting arrangement, having an output for the in-phase local oscillator signal, and applying a secondary frequency multiplication factor; and a second secondary frequency multiplier input from the second output of the phase-splitting arrangement, having an output for the quadrature local oscillator signal, and applying the secondary frequency multiplication factor.

Phased array transceiver element

A slope analog-to-digital converter, ADC, comprises: an input unit comprising a sampling capacitor, wherein the input unit is configured to during an initial period obtain a sampled value of an analog input signal and, during a conversion period, hold the sampled value across the sampling capacitor; and a comparator configured to determine a most significant bit of the analog input signal during the initial period; wherein the ADC during the conversion period is configured to receive a slope signal and to be adapted based on the determined most significant bit such that the comparator is further configured to adaptively compare the sampled value and the slope signal for converting the sampled value to a digital representation.

Slope analog-to-digital converter and a method for analog-to-digital conversion of an analog input signal

Example embodiments relate to time-interleaved analog-to-digital converters and conversion methods thereof. One embodiment includes a slope analog-to-digital converter. The slope analog-to-digital converter includes a sample and hold stage configured to sample an analog input signal at a sampling frequency. The slope analog-to-digital converter also includes a comparator downstream to the sample and hold stage configured to compare the analog input signal to a slope signal. Further, the slope analog-to-digital converter includes a digital logic configured to receive a counter value corresponding to a voltage level of the slope signal and to sample the counter value based upon the comparison, thereby generating a digital representation of the analog input signal based upon the comparison. The slope signal is asynchronous to the sampling frequency.

Time-interleaved analog-to-digital converter and conversion method thereof

A device for buffering a reference signal comprises a regulator circuit configured to generate at least two replicas of the reference signal as regulated output signals. The device further comprises a receiving circuit configured to receive the regulated output signals in a switchable manner. In this context, the regulated output signals are configured to have different performance characteristics.

Device and method for enhancing voltage regulation performance

An odd harmonic generation device is provided. The odd harmonic generation device includes an even harmonic generation unit and a mixer. In this context, the even harmonic generation unit is configured to generate two even harmonic signals on the basis of a fundamental signal. In addition to this, the mixer is configured to mix the fundamental signal with the two even harmonic signals to generate a desired odd harmonic signal.

Odd harmonic generation device and method

An successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes a digital-to-analog converter, a successive approximation register, a comparator, and a threshold voltage determining unit. In this context, the threshold voltage determining unit is configured to dynamically determine the threshold voltage of the comparator on the basis of the input signal of the digital-to-analog converter or the output signal of the comparator.

Advanced successive approximation register analog-to-digital converter and corresponding method

The method of calibrating a two-point modulation phase locked loop (PLL) comprises observing, between the loop filter and the second injection point, the loop control signal over at least one period of the first periodic control signal; generating, from the observed loop control signal, a distortion profile; and applying the distortion profile to the second periodic control signal before injecting the second periodic control signal in the PLL. Since, in the case of non-linearity in the controlled oscillator, the PLL output deviates from the ideally expected one, cancellation through the first injection point becomes imperfect disturbing the loop. This error pattern can be observed on the loop filter which allows to generate a distortion profile to distort the second periodic control signal for the next period of the modulation. This will mitigate the effects of the non-linearity of the oscillator.

Method of calibrating and a calibration circuit for a two-point modulation phase locked loop

An apparatus is provided for on-chip reconstruction of transient settling behavior. The apparatus comprises a first sampling circuit configured to sample a tracked analog signal output from a circuit under test over an operating period at a first sampling time, thereby generating a first sample output. In addition, the apparatus comprises a second sampling circuit configured to sample the tracked analog signal output at a second sampling time, thereby generating a second sample output. The apparatus further comprises a signal subtraction circuit configured to perform subtraction of the first sample output and the second sample output, thereby generating a difference signal. Moreover, the apparatus comprises a signal conversion circuit configured to output the difference signal in the digital domain.

Apparatus and method for on-chip reconstruction of transient settling behavior

A digital radio-frequency (RF) circuitry is disclosed. In one aspect, the circuitry includes a digitally controlled amplifier configured to receive an RF input signal and a digital control signal, and to output an amplitude controlled output signal. The digitally controlled amplifier includes one or more common-source amplifying unit cells. A respective common-source amplifying unit cell includes a sources node connected to a switching circuitry controllable by the digital control signal so as to activate or deactivate the common-source amplifying unit cell. The switching circuitry comprises a first switch configured to connect the source node with a first power supply node and a second switch configured to connect the source node with a second power supply node when activating and deactivating, respectively, the common-source amplifying unit cell.

Digital radio frequency circuitry

A multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter is disclosed. In one aspect, the circuit comprises an input block including a capacitor and arranged for switchably connecting a first terminal of the capacitor to an input voltage signal during a first phase and to a fixed reference voltage during a second phase, a sub-analog-to-digital conversion circuit connected to a second terminal of the capacitor and arranged for quantizing a voltage on the capacitor during the second phase, a sub-digital-to-analog conversion circuit that receives the quantized version of the voltage and outputs an analog voltage derived from the quantized version, a feedback block including an amplifier connected to the second terminal of the capacitor and producing, at an amplifier output during a third phase, a residue signal corresponding to a combination of the input voltage signal and the analog voltage, and a feedback circuit.

Multiplying digital-to-analog conversion circuit

The disclosed technology relates to a method for improving performance of a feedback circuit comprising an amplifier and a feedback network, wherein the feedback circuit has at least one tunable component. In one aspect, the method comprises measuring first amplitude values at an input of the amplifier and second amplitude values at an output of the amplifier, estimating a linear open-loop gain of the amplifier based on both the amplitude values, estimating a linear finite gain error based on the estimated gain and the second amplitude values, subtracting the linear finite gain error from the first amplitude values to derive a set of samples containing second error information, deriving an signal-to-noise-plus-distortion ratio estimate based on the variance of the set of samples and a variance of the second amplitude values, and adjusting the feedback circuit in accordance with the signal-to-noise-plus-distortion ratio estimate.

Method for improving feedback circuit performance

A polar transmitter provided for transmitting a phase/frequency modulated and amplitude modulated transmit signal and a method for generating a transmit signal using a polar transmitter are described. An example polar transmitter comprises a phase locked loop for generating a phase/frequency modulated precursor of the transmit signal. The phase locked loop comprises at its input a phase error detection unit for detecting a phase error of the precursor fed back from the output of the phase locked loop to the phase error detection unit as a feedback signal. The polar transmitter comprises a digital amplitude modulator for amplitude modulation of the precursor, resulting in the transmit signal. The digital amplitude modulator is arranged within the phase locked loop for amplitude modulation of the precursor before being output by the PLL. The phase error detection unit is further provided for detecting the amplitude of the feedback signal.

Polar transmitter and method for generating a transmit signal using a polar transmitter

A SAR DAC architecture is disclosed. In one aspect, the SAR DAC architecture uses two parallel DACs for performing a comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator. For fast operation, the comparator performs the comparison with a reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by a previous comparison step. As a result, the same delay can be used for each DAC feedback and comparison, reducing the total conversion time to the time needed for N comparisons for an N-bit architecture, which is a reduction of almost a factor of 2 compared to the conventional SAR architecture.

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Boutersem, Belgium

Jan Craninckx