Sun Microsystems, Inc.

International Business Machines Corporation

Google Inc.

Cisco Technology, Inc.

Pensando Systems Inc.

Jan Civlin

Itai Nahshon

Matthew Nicholas Papakipos

Brian K Grant

Christopher G Demetriou

Kalman Zvi Meth

Nathan Daniel Tuck

Joe Epstein

Bilha Mendelson

Maksim V Panchenko

David Bernstein

Gadi Haber

Methods and systems for distributing instructions amongst processing units in a processing pipeline are disclosed. A method includes compiling a set of instructions for a stage of a multistage programmable processing pipeline in which the stage of the multistage programmable processing pipeline includes multiple processing units configured to processes instructions in parallel, wherein compiling the set of instructions includes, identifying first and second subsets of instructions within the set of instructions that can be executed independent of each other, assigning the first subset of instructions to a first processing unit of the stage, assigning the second subset of instructions to a second processing unit of the stage, and executing the first and second subsets of instructions in parallel at the first and second processing units, respectively.

Methods and systems for distributing instructions amongst multiple processing units in a multistage processing pipeline

In one embodiment, methods are described to provide a binary translation and randomization system. Relocation metadata is received, which comprises, for each of a plurality of execution units in an executable file, a mapping from the executable file into an address space range. For at least one of the plurality of execution units, the mapping is modified to replace instructions within the address space range with a relocated copy of the instructions at a randomly located address space range. An order of the plurality of execution units may thus be modified. An image is generated from the executable file using the relocation metadata, and an execution of the image is caused. The randomization may be carried out in two passes to provide executable files that are uniquely randomized for each computer and for each execution.

Binary translation and randomization system for application security

A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of the parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. A profiling tool is used to collect, analyze, and visualize the performance data of an application in connection with its execution on a parallel-processing computer system through the runtime system. This profiling tool greatly enhances an application developer's ability to understand how an application is executed on the parallel-processing computer system and fine-tune the application to achieve high performance.

Systems and methods for profiling an application running on a parallel-processing computer system

In a method for execution control acquisition of a program, during the execution of the program, it is determined when a hardware performance counter has reached a threshold. When the threshold is reached, execution control is switched to a dynamic optimizer. Thereafter, an optimized version of the program is executed. In a method for executing an optimized version of a program, during execution of the optimized version, an interrupt is received and execution control is returned to an operating system. An original version of the program is then executed. During the execution of the original version, a hardware performance counter is monitored. When the hardware performance counter reaches a threshold during the execution of the original version, execution control is switched to a dynamic optimizer. Thereafter, the execution of the optimized version of the program is continued as directed by the dynamic optimizer.

Methods for execution control acquistion of a program and for executing an optimized version of a program

A method is provided for safely editing a binary code to be executed on a computer system. The method allows the binary code to be directly edited without compromising its integrity. More specifically, a larger binary code is transformed into a number of smaller binary code segments having sizes within a reference range of a control transfer function such as a branch instruction. A branch slamming operation can then used to displace a binary instruction contained within a smaller binary code segment with a branch instruction referring to a binary patch that is appended to the smaller binary code segment. The binary instruction displaced by the branch instruction is preserved in the binary patch. Upon completion of the binary patch execution, the smaller binary code segment continues executing with a binary instruction immediately following the branch instruction. The method for safely editing the binary code is particularly useful with large binary codes having sizes greater than the reference range of the control transfer function.

Method for safely instrumenting large binary code

In a method for dynamic allocation of memory address space, an original version of a program is executed. This execution includes the execution of a request to use memory address space occupied by an optimized version of the program that is protected from modification. When this request is detected, execution control is passed to an optimization code that was used to define the optimized program. The optimization code copies a portion of the optimized program residing in the memory address space requested by the original program, writes the copied portion to unallocated memory address space, and adjusts the code of the optimized program. The protection of the copied portion of the optimized program is released, and execution control is returned to the original program. The request to use the memory address space occupied by the portion of the optimized for which the protection has been released is then re-executed.

Methods and hardware for safe memory allocation in arbitrary program environments

One embodiment of the present invention provides a system that facilitates prefetching memory pages for a computer program. The system operates by analyzing the computer program within a compiler to identify memory pages accessed within a portion of the computer program. Next, the system creates a map of these memory pages accessed by the computer program, wherein the map is indexed by a program counter for the computer program. A given program counter value indexes memory pages within this map that are likely to be accessed during subsequent execution of the computer program. The system examines the map during execution of the computer program, and if the current program counter for the computer program indexes memory pages in the map, the system touches the memory pages, thereby causing the system to prefetch the memory pages.

Method and apparatus for prefetching memory pages during execution of a computer program

A processor includes a tagging buffer for storing information that advises the processor of potential memory collisions caused by program instruction pairs that refer to the same memory address. In one method for avoiding memory collisions, a program having tagging code identifying program instruction pairs of the program that refer to a same memory address is compiled. The program instruction pairs in the compiled program code are processed while verifying an order in which the program instruction pairs are to be executed using the compiled tagging code, which is loaded into a tagging buffer. In another method, a program that does not include tagging code is compiled. When a trap occurs in the processing of a program instruction pair, program counters that cause the instructions to be executed in a desired order are added to a tagging buffer. A computer system including the processor also is described.

Processor with tagging buffer and methods for avoiding memory collisions

One embodiment of the present invention provides a system for controlling cache line eviction. The system operates by first receiving a sequence of instructions at a processor during execution of a program, wherein the sequence of instructions causes a cache line to be loaded into the cache. Next, the system examines the sequence of instructions to determine if an associated cache line includes only scratch data that will not be reused. If so, upon loading the cache line into the cache, the system marks the cache line as containing only scratch data, which allows the cache line to be evicted next from the cache.

Method and apparatus for controlling line eviction in a cache

One embodiment of the present invention provides a system that facilitates speculative execution of instructions within a computer system. Upon encountering a stall during execution of an instruction stream, the system synchronizes a cache containing data that is being operated on by the instruction stream. Next, the system configures the cache so that the cache operates as before except that changes to cache lines are not propagated to lower levels of the memory system. The system then speculatively executes a subsequent portion of the instruction stream without waiting for the event that caused the stall to be resolved. In this way, the speculative execution can only change data within the cache, and these changes are not propagated to lower levels of the memory system unless a subsequent commit operation takes place.

Method and apparatus for using a non-committing data cache to facilitate speculative execution

A CPU includes a register file including a plurality of architectural registers for storing data loaded from a primary memory for execution by the CPU. A stack cache memory coupled to the register file includes a plurality of cache lines, each of which corresponds to one of the architectural registers and implements a first-in, last-out queue for data spilled from the corresponding architectural register. Data spilled from the register file into the stack cache memory is maintained in the stack cache until subsequently restored to the register file without accessing primary memory. The stack cache memory does not participate in cache writeback operations to primary memory.

Register stack in cache memory

A technique for statically linking an application process to a wrapper library employed in intercepting one or more calls invoked by the application process. The intercepted calls may comprise system calls or library calls. In a first link step, the application process is statically linked with at least the intercept library, and in one embodiment, all libraries associated with the application process except for the wrapper library. This first statically linking step creates a first module. Thereafter, at least one call invoked by the application process, and to be intercepted by the intercept library, is renamed. The renaming of the intercepted call is from its original name to a temporary name in the standard program library, the intercept library and the application program. This renaming step creates a second module that no longer contains the original name of the at least one intercepted call. The second linking step is to statically link the second module with the wrapper library, thereby creating an executable module wherein the application process is statically linked to all libraries while still providing for interception of the at least one system or library call within the executable.

Statically linking an application process with a wrapper library

A method for effecting a direct jump in an executable program module to a target address displaced from a source address by a specified distance that is greater than a maximum permitted range. During program linkage the direct jump is split into at least two component direct jumps each no greater than the maximum permitted range, thus allowing the direct jump to be achieved by jumping sequentially from the source address to the target address via each of the component direct jumps. A storage medium for storing data representative of the executable program module contains at least one trampoline for performing the component direct jumps.

Growing community of inventors

Sunnyvale, CA, United States of America

Jan Civlin