Intel Corporation

Other

Jamison D Collins

Hong Wang

Perry H Wang

James Paul Held

John P Shen

Edward Thomas Grochowski

Partha Kundu

Tin-Fook Ngai

Raya Leviathan

Gautham N Chinya

Sebastian Winkel

John Thomas Shen

Jayesh Iyer

Per H Hammarlund

Prashant Sethi

Richard A Hankins

Ajay V Bhatt

Ethan Schuchman

Jason M Agron

Polychronis Xekalakis

Deepak A Mathaikutty

Howard Chen

Stephen F Whalley

Christopher J Hughes

Hong Jiang

Guei-Yuan Lueh

Gad Shlomo Sheaffer

Koichi Yamada

Xinmin Tian

Ralph Michael Kling

Asit K Mallick

Bryan P Black

Daniel M Lavery

Girish Venkatasubramanian

Yong-fong Lee

Tyler N Sondag

Bernard Lint

Ed Grochowski

Rupert Brauch

Natalie D Enright

Xinmin Tran

Ralph M King

Michael D Linderman

Howard H Chen

A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

Instruction and logic for predication and implicit destination

Methods and apparatuses relating to preventing the execution of a modified instruction. In one embodiment, an apparatus includes a hardware binary translator to translate an instruction to a translated instruction, and a consistency hardware manager to prevent execution of the translated instruction by a hardware processor on detection of a modification to a virtual to physical address mapping of the instruction after the translation.

Apparatuses and methods to prevent execution of a modified instruction

A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

Method and system to provide user-level multithreading

In one embodiment, a processor includes logic, responsive to a first instruction, to perform an operation on a first source operand and a second source operand associated with the first instruction and write a result of the operation to a destination location comprising a third source operand. The write may be a partial write of the destination location to maintain an unmodified portion of the third source operand. Other embodiments are described and claimed.

Performing partial register write operations in a processor

A processing device includes a store instruction identification unit to identify a pair of store instructions among a plurality of instructions in an instruction queue. The pair of store instructions include a first store instruction and a second store instruction. The first data of the first store instruction corresponds to a first memory region adjacent to a second memory region, and a second data of the second store instruction corresponds to the second memory region. The processing device to include a store instruction fusion unit to fuse the first store instruction with the second store instruction resulting in a fused store instruction.

Fused adjacent memory stores

In one embodiment, a processor includes a front end unit to fetch and decode an instruction. The front end unit includes a first random number generator to generate a random value responsive to a profileable event associated with the instruction. The processor further includes a profile logic to collect profile information associated with the instruction responsive to a sample signal, where the sample signal is based on at least a portion of the random value. Other embodiments are described and claimed.

Providing deterministic, reproducible, and random sampling in a processor

Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution

In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Providing hardware support for shared virtual memory between local and remote physical memory

In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer, detecting the assertion signal in the accelerators and communicating a request for a lock, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer. Other embodiments are described and claimed.

Processor for enabling inter-sequencer communication following lock competition and accelerator registration

Growing community of inventors

Los Gatos, CA, United States of America

Jamison D Collins