Akeana, Inc.

James Youngsae Cho

Rabin Sugumar

Chandramouli Banerjee

Disclosed embodiments provide techniques for branch prediction. A processor core is accessed. The processor core is coupled to memory and includes branch prediction circuitry. The branch prediction circuitry includes a branch target buffer (BTB) and an indirect branch target buffer (BTBI). A hashed program counter within the processor core is read. The BTB and BTBI are searched. The searching the BTB is accomplished with the hashed program counter and the searching the BTBI is accomplished with the hashed program counter and branch history information. A predicted branch target address within the BTBI or the BTB is matched. The matching within the BTBI is based on an indirect branch instruction, and the matching within the BTB is based on other branch instruction types. The predicted branch target address that was matched is predicted taken. The processor core is directed to fetch a next instruction from the predicted branch target address.

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James Youngsae Cho