Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Inc.

National University of Singapore

James Yongmeng Lee

Lap Chan

Huang Liu

Elgin Kiok Quek

Hong Yu

Alex See

Jia Zhen Zheng

Yang Pan

Yelehanka Ramachandramurthy Pradeep

Ying Keung Leung

Ravi Sundaresan

Chung Woh Lai

Zhao Lun

Johnny Widodo

Liang-Choo Hsia

Wang Ling Goh

Shailendra Mishra

Victor Seng Keong Lim

Alex K H See

Ganesh S Samudra

Francis YongWee Poh

Chen Feng

Wenzhi Gao

Yongsik Moon

Sneedharan Pillai Sneelal

C K Lau

Wang Haiting

A method for enabling fabrication of RMG devices having a low gate height variation and a substantially planar topography and resulting device are disclosed. Embodiments include: providing on a substrate two dummy gate electrodes, each between a pair of spacers; providing a source/drain region between the two dummy gate electrodes; and forming a first nitride layer over the two dummy gate electrodes and the source/drain region, wherein the first nitride layer comprises a first portion over the dummy gate electrodes and a second portion over the source/drain region, and the second portion has an upper surface substantially coplanar with an upper surface of the dummy gate electrodes.

Method and device to achieve self-stop and precise gate height

An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.

Integrated circuit system employing selective epitaxial growth technology

A method for forming a self-aligned, recessed channel, MOSFET device that alleviates problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A thin pad oxide layer is grown overlying the substrate and a gate recess, followed by deposition of a thick silicon nitride layer filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown, thickening the pad oxide layer. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is removed. The oxide layer at the bottom of the gate recess is removed and a gate dielectric layer is grown. Gate polysilicon is deposited filling the gate recess. S/D implantations, metallization, and passivation complete fabrication of the device.

Process flow for a performance enhanced MOSFET with self-aligned, recessed channel

A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners. The second etch stop layer is polished away until the oxide layer overlying the first etch stop layer is exposed. The exposed oxide layer overlying the first etch stop layer is removed. The first and second etch stop layers are removed to complete the planarized shallow trench isolation regions in the manufacture of an integrated circuit device.

Method to achieve STI planarization

A method of fabrication of an elevated source/drain (S/D) for a MOS device. A first insulating layer having a gate opening and source/drain openings is formed over a substrate. We form a LDD resist mask having opening over the source/drain openings over the first insulating layer. Ions are implanted through the source/drain openings. A first dielectric layer is formed on the substrate in the gate opening and source/drain openings. A gate is formed in the gate opening and raised source/drain (S/D) blocks in the source/drain openings. We remove the spacer blocks to form spacer block openings. We form second LDD regions by implanting ions through the spacer block openings. We form second spacer blocks in the spacer block openings. Plug opening are formed through the raised source/drain (S/D) blocks. Contact plugs are formed in the form plug opening.

Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide

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Singapore, Singapore

James Yongmeng Lee