International Business Machines Corporation

Infineon Technologies Ag

Infineon Technologies North America Corp.

Marvell International Limited

James Wilson Rae

William G Bliss

Razmik Karabed

Jonathan James Ashley

Stephen James Franck

Heinrich J Stockmanns

Paul H Siegel

Hemant K Thapar

Lyle J Fredrickson

Heiner Stockmanns

Fritz Mistlberger

Sasan Cyrusian

Earl Albert Cunningham

Roger William Wood

Elmar Bach

Thomas Blon

Kaichi Zhang

Michael A Ruegg

Siegfried Hart

Matthias Driller

Townsend H Porter, Jr

Gregory J Kerwin

Dat Nguyen

Ulrich Huewels

Sriharsha Annadore

Dominik Margraf

Stephen J Franck

Michael Ruegg

An improved Viterbi detector is disclosed in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. Also disclosed is a method of reducing the complexity of the branch metric calculations by clustering branches corresponding to signals with similar signal-dependent noise statistics. A feature of this architecture is that the branch metrics (and their corresponding square difference operators) are clustered into multiple groups, where all the members of each group draw input from a single, shared noise predictive filter corresponding to the group. In recording technologies as practiced today, physical imperfections in the representation of recorded user data in the recording medium itself are becoming the dominate source of noise in the read back data. This noise is highly dependent on what was (intended to be) written in the medium. The disclosed Viterbi detector exploits this statistical dependence of the noise on the signal.

Method and apparatus for a data-dependent noise predictive viterbi

Systems and methods for reading information stored on a magnetic medium are described. Data symbols are generated from a signal encoded at a baud rate with data including an acquisition preamble defining an acquisition frequency and an acquisition phase. The system includes an inventive dual loop synchronizer that is optimized to improve the operating efficiency and reduce the overall latency of the read channel. In one aspect, the dual loop synchronizer includes a frequency synchronization loop, a signal sampler, an interpolator, and a phase synchronization loop. The frequency synchronization loop is configured to generate a sampling clock synchronized approximately to the acquisition frequency and the acquisition phase of the encoded data signal. The signal sampler is coupled to the frequency synchronization loop and is configured to sample the encoded data signal in response to the sampling clock to produce a plurality of data samples. The interpolator is coupled to the frequency synchronization loop and is configured to produce in response to the sampling clock interpolated samples from the data samples. The phase synchronization loop is coupled to the interpolator and is configured to synchronize the interpolator to the baud rate of the encoded data signal. In another aspect, the frequency synchronization loop includes a delay-locked loop configured to synthesize the sampling clock.

Pseudo-synchronous interpolated timing recovery for a sampled amplitude read channel

A method and apparatus for handling end of data processing in a data storage device. The method includes receiving a plurality of user data bits at a write channel. The method further includes appending primary padding bits to user data bits if the plurality of user data bits is less than a multiple of an input block length of an encoder in the write channel and encoding the plurality of user data bits and any primary padding bits into a plurality of encoded data bytes. Additionally, the method includes appending an end of data marker to an end of the plurality of encoded data bytes, wherein the end of data marker has a length of no more than one byte, and writing the plurality of encoded data bytes and the end of data marker to the data store.

Method and apparatus for handling end of data processing in a data storage device

A method and apparatus for Viterbi detector state metric re-normalization. The method includes fabricating a Viterbi detector ( ) having a predetermined number of states, wherein the Viterbi detector ( ) stores a state metric value and a branch metric value for each state, and wherein the Viterbi detector ( ) implements a trellis diagram. The method includes constructing a Viterbi detector ( ) which can support a state metric value having g&plus;h&prime; number of bits. The number of bits needed to represent the branch metric value is represented by (g) and the additional number of bits needed to represent the state metric value is represented by (h&prime;). The additional number of bits (h&prime;) is less than the additional number of bits (h) determined using the following inequality: 2 &minus;h&gE;K&minus;1, wherein K represent the constraint length of the trellis diagram.

Method and apparatus for Viterbi detector state metric re-normalization

An apparatus and method for adding errors to magnetic data and then detecting the errors is revealed. The method includes providing a magnetic recording channel, reading and digitizing a stored signal, introducing an error signal that emulates off-track interference, adding the error to the digitized signal, and determining an error rate. The apparatus includes a magnetic recording channel having a linear feedback shift register to generate a pseudo-random binary sequence, circuitry to convert the sequence into an error signal, and a Viterbi detector to quantify an error rate.

Off-track interference emulator

A method and apparatus to optimize a bit error rate for a partial response, maximum likelihood (&ldquo;PRML&rdquo;) read/write channel is disclosed. A channel margining circuit that is configured to carry out an embodiment for a method of optimizing the bit error rates of a read/write channel is described. The margining circuit derives an interference signal to stress a read/write channel for optimizing the bit error rate. The signal is derived from bit errors inherent with the read/write channel. The circuit reduces the time to optimize the channel by providing an amplified interference signal that increases a bit error rate during optimization.

Total error multiplier for optimizing read/write channel

A method and apparatus for running an analog portion ( ) of a read/write channel ( ) from a highly regulated power supply ( ). The apparatus includes an analog portion ( ), a clock synthesizer ( ), and a highly regulated power supply ( ) connected to the analog portion ( ) and the clock synthesizer ( ). The analog portion ( ) and the clock synthesizer ( ) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply ( ) supplies power that is within the first voltage range to the analog portion ( ) and the clock synthesizer ( ). The method includes generating power that is within the first voltage range using the highly regulated power supply ( ), and supplying the power to the analog portion ( ) and the clock synthesizer ( ).

Efficient analog front end for a read/write channel of a hard disk drive running from a highly regulated power supply

Systems and methods for accumulating data relating to the performance of one or more components of a read channel are described. In one aspect, a programmable channel quality monitor is operable to accumulate performance data corresponding to a recorded test data sequence spanning two or more data sectors of the magnetic medium. The channel quality monitor preferably is incorporated in a disk drive system. A method of accumulating performance data from a read channel also is described. In accordance with this inventive method, an original test data pattern is written to multiple data sectors of the magnetic medium. The original test pattern is read from the multiple data sectors of the magnetic medium to produce a readback test pattern. In this method, performance data relating to a comparison of the original test pattern and the readback test pattern is accumulated.

Accumulating read channel performance data

An improved sampled amplitude read/write channel is provided. The system is an integrated Generalized Partial Response Maximum Likelihood (GPRML) read channel incorporating Read, Write, and Servo modes of operation. One implementation includes a 32/34 rate parity code and matched Viterbi detector, a 32 state Viterbi detector optimal parity processor, robust frame synchronization, self-adaptive equalization, thermal asperity detection and compensation, adaptive magneto-resistive asymmetry compensation, low latency interpolated timing recovery and programmable write precompensation.

Read/write channel

A magneto-resistive asymmetry compensation system includes a linearizer ( ) interposed in a data path and a control loop ( ). The control loop uses signal estimates from an interpolated timing response unit ( ) to derive a magneto-resistive asymmetry error. The error term is used to obtain a control scaling input to the linearizer. The linearizer functions to multiply the scaling multiple to the square of the input signal and then add it back to the input signal.

Magneto-resistive asymmetry compensation loop

A first trellis code ( A, A) according to the present invention is a rate 24/26 trellis code with three (3) bytes error propagation due to EPRML minimum instance channel errors, a minimum of six (6) transitions per code word and a maximum of twelve (12) consecutive zeroes. A second trellis code ( B, B) according to the present invention is a rate 48/51 trellis code, derived from the first trellis code. The second trellis code has four (4) bytes error propagation due to EPRML minimum distance channel errors, a minimum of twelve (12) transitions per code word and a maximum of twelve (12) consecutive zeroes. A third trellis code ( C, C) according to the present invention is a rate 48/51 trellis code with four (4) bytes error propagation due to EPRML minimum distance channel errors, a minimum of fourteen (14) transitions per code word and a maximum of eleven (11) consecutive zeroes.

Trellis code for extended partial response maximum likelihood (EPRML) channel

Apparatus and method for transmitting spectral null sequences of a spectrally-constrained code over a partial response channel. A Viterbi detector receives the sequences from the channel and has a time-varying detector trellis structure derived from a running-digital-sum (RDS) trellis structure that requires each one of a set of quasicatastrophic sequences to be generated only from a trellis state corresponding to a respective preselected unique RDS value.

Matched spectral null codes with partitioned systolic trellis structures

Viterbi trellis coding methods and Viterbi detector apparatus are provided for detecting trellis coded data. A systolic array Viterbi detector recursively calculates path metrics and partial sums of metric update equations to determine codeword sequences having minimum mean squared error for Viterbi-type maximum-likelihood data detection. The systolic array Viterbi detector is arranged to eliminate redundant calculations and simplify hardware requirements. Modified butterfly trellis geometries and rotating state metrics arrangements are provided for simplifying the Viterbi detector.

Viterbi trellis coding methods and apparatus for a direct access storage

A method and apparatus for detecting spectral null sequences of a spectrally-constrained code on a noisy communications channel. From a Viterbi detector with a trellis structure comprising a plurality of states and edges, predetermined ones of the states and edges in the trellis structure are deleted at preselected times modulo N, such as times .phi. modulo N and/or at intermediate times m modulo N, where m=.phi., thereby to create a time-varying trellis structure for limiting the maximum length of dominant error events. The deleted edges are generally those edges which would have entered or emanated from the deleted states if they were not deleted. The trellis structure may be a so-called systolic structure, in which case the spectral null sequences are preferably DC-free or Nyquist free.

Growing community of inventors

Rochester, MN, United States of America

James Wilson Rae