International Business Machines Corporation

James Wilson Bishop

Dung Q Nguyen

Hung Qui Le

Marcy Evelyn Byers

Brian William Thompto

Brian David Barrick

Sundeep Chadha

David R Terry

Mary Douglass Brown

Jafar Nahidi

Robert Allen Cordes

Philip Lee Vitale

Gregory Robert Klouda

Stefan P Jackowski

Robert D Siegl

Balaram Sinharoy

Jing Zhang

Joel Abraham Silberman

Maarten Jakob Boersma

Michael Joseph Genden

Jentje Leenstra

William Elton Burky

Maureen Anne Delaney

Cliff Kucharski

Jeffrey Carl Brownscheidle

Todd Alan Venton

Raymond Cheung Yeung

Steven Bradford Herndon

Patrick W Gallagher

George A Fax

Robert G Iseminger

Charles Embrey Carmack, Jr

Steven R Carlough

Michael Stephen Floyd

Susan Elizabeth Eisen

Phillip G Williams

Albert James Van Norstrand, Jr

Christopher Michael Abernathy

Alexander Erik Mericas

Scott Barnett Swaney

Steven J Battle

Jose Angel Paredes

Michael Thomas Vaden

Niels Fricke

Benjamin W Stolt

Robert Dominick Mirabella

Michael James Mack

Wolfram Sauer

Maria Lorena Pesantez

Mark Louis Ciacelli

Paul M Kennedy

David Henry Wilde

Dan Buerkle

Patrick Wayne Gallagher

A computer-implemented method for of constrained carries on speculative counters includes providing one or more speculative counters having an upper portion of most significant bits partially embedded in a random-access memory (RAM) array, and a pre-counter portion external to the RAM array having a plurality of least significant bits. The one or more speculative counters are configured to count a plurality of events of interest during a processor core instruction execution. A carry output from the pre-counter portion to the RAM array is suppressed for a duration of a speculative event period.

Constrained carries on speculative counters

Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.

Operation of a multi-slice processor implementing a hardware level transfer of an execution thread

A processor configured to manage a transaction memory (TM) state. The processor is configured to receive a first instruction indicating a start of a speculative transaction and update a register file with a speculative transaction memory (TM) state corresponding to the speculative transaction. The processor is further configured to determine whether or not the register file is able to store the entirety of speculative TM state. If the register file is unable to store the entirety of the speculative TM state, the processor is configured to copy a previous TM (pre-TM) state from the register file to a memory which is external to the processor. Further, the processor may be configured to complete updating the register file with the speculative TM state after the pre-TM state has been copied from the register file to the memory.

Saving and restoring a transaction memory state

Methods and apparatus for thread migration using a microcode engine of a multi-slice processor including issuing a thread migration instruction to the microcode engine of a decode unit, the thread migration instruction comprising an indication that the thread migration instruction is to be processed by the microcode engine; decoding, by the microcode engine, the thread migration instruction into a plurality of internal operations each targeting a different register entry; transmitting the plurality of internal operations to a dispatcher of the multi-slice processor; and manipulating, by the multi-slice processor, a plurality of register entries according to the plurality of internal operations.

Thread migration using a microcode engine of a multi-slice processor

Techniques for error correction in a processor include detecting an error in first data stored in a register. The method also includes generating an instruction to read the first data stored in the register, where the register is both a source register and a destination register of the instruction. The method further includes transmitting the first data to an execution unit, where the first data bypasses an issue queue. The method also includes decoding the instruction and correcting the error to generate corrected data and writing the corrected data to the destination register.

ECC scrubbing method in a multi-slice microprocessor

A supervisory hardware device in a processor core detects a flush instruction that, when executed, flushes content of one or more general purpose registers (GPRs) within the processor core. The content of the one or more GPRs is moved to a history buffer (HB) and an instruction sequencing queue (ISQ) within the processor core, where the content includes data, an instruction tag (iTag) that identifies an instruction that generated the data, and error correction code (ECC) bits for the data. In response to receiving a restore instruction, the supervisory hardware device error checks the data in the ISQ using the ECC bits stored in the ISQ. In response to detecting an error in the data in the ISQ, the supervisory hardware device sends the data and the ECC bits from the ISQ to an ECC scrubber to generate corrected data, which is restored into the one or more GPRs.

In-pipe error scrubbing within a processor core

Techniques for error correction in a processor include detecting an error in first data stored in a register. The method also includes generating an instruction to read the first data stored in the register, where the register is both a source register and a destination register of the instruction. The method further includes transmitting the first data and error correcting code data to an execution unit, where the first data and error correcting code data bypasses an issue queue. The method also includes decoding the instruction and correcting the error to generate corrected data and writing the corrected data to the destination register.

ECC scrubbing in a multi-slice microprocessor

According to one embodiment of the present disclosure, an approach is provided in which a thread is selected from multiple active threads, along with a corresponding weighting value. Computational logic determines whether one of the multiple threads is dispatching an instruction and, if so, computes a dispatch weighting value using the selected weighting value and a dispatch factor that indicates a weighting adjustment of the selected weighting value. In turn, a resource utilization value of the selected thread is computed using the dispatch weighting value.

Region-weighted accounting of multi-threaded processor core according to dispatch state

An approach is provided in which a thread is selected from multiple active threads, along with a corresponding weighting value. Computational logic determines whether one of the multiple threads is dispatching an instruction and, if so, computes a dispatch weighting value using the selected weighting value and a dispatch factor that indicates a weighting adjustment of the selected weighting value. In turn, a resource utilization value of the selected thread is computed using the dispatch weighting value.

An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store (IDS). The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update.

Processor including age tracking of issue queue instructions

A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors

An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power.

Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue logic determines that the unified payload does not include a load-store instruction that is ready to issue. As a result, the issue logic issues the simple fixed point instruction to the load-store execution unit in response to determining that the simple fixed point instruction is ready to issue and determining that the unified payload does not include a load-store instruction that is ready to issue.

Selecting fixed-point instructions to issue on load-store unit

An information handling system includes a processor with a bifurcated unified issue queue that may perform unified issue queue VSU store instruction dependency operations. The bifurcated unified issue queue BUIQ maintains VSU store instructions in the form of internal operations data. The BUIQ includes a unified issue queue UIQand a unified issue queue UIQ. The BUIQ may manage a particular VSU store instruction from one UIQ to determine data dependencies and employ the other UIQ to determine address dependencies of that particular VSU store instruction. The UIQs employ a dependency matrix including a dependency array. The dependency array data maintains both data and address dependency information. The particular VSU store instruction issues to execution units such as VSUs for data dependency information and load store units (LSUs) for address dependency information. A particular VSU store instruction may execute to provide data dependency information independent of address dependency information.

Information handling system including a processor with a bifurcated issue queue

Growing community of inventors

Newark Valley, NY, United States of America

James Wilson Bishop