International Business Machines Corporation

James William Van Fleet

Bruce Gerard Mealey

Andrew Dunshea

Dirk Michel

Jos Manuel Accapadi

Michael Stephen Williams

David William Mehaffy

Larry Bert Brenner

Mark Edward Dean

Mysore Sathyanarayana Srinivas

Guy G Sotomayor

Ronald Lynn Rockhold

Greg Robert Mewhinney

James Michael Magee

Bimal Kiran Doshi

A system and method is provided for delaying a priority boost of an execution thread. When a thread prepares to enter a critical section of code, such as when the thread utilizes a shared system resource, a user mode accessible data area is updated indicating that the thread is in a critical section and, if the kernel receives a preemption event, the priority boost that the thread should receive. If the kernel receives a preemption event before the thread finishes the critical section, the kernel applies the priority boost on behalf of the thread. Often, the thread will finish the critical section without having to have its priority actually boosted. If the thread does receive an actual priority boost then, after the critical section is finished, the kernel resets the thread's priority to a normal level.

System and method for delayed priority boost

A system and method is provided for measuring lock usage in a non-intrusive manner. Measurements are performed only when a lock is contended. When a lock is requested and the lock is available (i.e., is not contended), the only data gathered is a counter that is incremented to keep track of the number of times the particular lock was requested. When a lock is contended, an operating system trace hook is requested. The trace hook records data such as the timestamp that the requester requested the lock, the request count, a stack traceback to identify the function corresponding to the requester, and the address of the lock that was requested. Post-operative processing analyzes the recorded trace hook data to identify contended locks and processes that may not be efficiently using locks.

System and method for measuring latch contention

A method for substantially reducing the latency of the database (DB) logging process by removing the agent notification requirement from the DB logger and allowing the DB logger to proceed to the next commit process without the latency of providing each waiting agent a notification that the agent continue their respective processes. When an agent commits a change to persistent storage of the database, the request is received by the logger, which performs the update to the persistent storage. A list of agents waiting on the completion of the commit process is compiled by the logger. The list of agents is provided to and provided to the next committing agent. The next committing agent then notifies the waiting agents that they are able to proceed with their respective processing. The logger may immediately perform the next update to persistent memory without utilizing a substantial amount of time notifying the waiting agents.

Method for improving the performance of database loggers using agent coordination

A system and method for thread scheduling with a weak preemption policy is provided. The scheduler receives requests from newly ready work. The scheduler adds a 'preempt value' to the current work's priority so that it is somewhat increased for preemption purposes. The preempt value can be adjusted in order to make it more, or less, difficult for newly ready work to preempt the current work. A 'less strict' preemption policy allows current work to complete rather than interrupting the current work and resume it at a later time, thus saving system overhead. Newly ready work that is queued with a better priority than the current work is queued in a favorable position to be executed after the current work is completed but before other work that has been queued with the same priority of the current work.

System and method for thread scheduling with weak preemption policy

System for delaying priority boost in a priority offset amount only after detecting of preemption event during access to critical section

A system and method is provided for measuring lock usage in a non-intrusive manner. Measurements are performed only when a lock is contended. When a lock is requested and the lock is available (i.e., is not contended), the only data gathered is a counter that is incremented to keep track of the number of times the particular lock was requested. When a lock is contended, an operating system trace hook is requested. The trace hook records data such as the timestamp that the requestor requested the lock, the request count, a stack traceback to identify the function corresponding to the requestor, and the address of the lock that was requested. Post-operative processing analyzes the recorded trace hook data to identify contended locks and processes that may not be efficiently using locks.

A system and method is altering the priority of a process, or thread of execution, when the process acquires a software lock. The priority is altered when the lock is acquired and restored when the process releases the lock. Thread priorities can be altered for every lock being managed by the operating system or can selectively be altered. In addition, the amount of alteration can be individually adjusted so that a process that acquires one lock receive a different priority boost than a process that acquires a different lock. Furthermore, a method of tuning a computer system by adjusting lock priority values is provided.

System and method for adding priority change value corresponding with a lock to a thread during lock processing

An improved system and method for improving complex storage locks that manage access to a shared resource. A FIFO queue is maintained for processes waiting to read or write to the shared resource. When the shared resource is available, the first item is read from the queue. If the first item is a write requestor, the requestor is woken up in order to request the lock. If the first item on the queue is a read requestor, then that read requestor is woken up along with any other read requestors read from the queue until a write requestor is encountered or the end of the queue is reached. When the write wanted flag is set, new read requestors are denied access to the read lock, however any read requestors that were woken up in order to use the read lock are granted a read lock.

System and method for improved complex storage locks

A method and system in a distributed shared-memory data processing system are disclosed having a single operating system being executed simultaneously by a plurality of processors included within a plurality of coupled processing nodes for determining a utilization of each memory location included within a shared-memory included within each of the plurality of nodes by each of the plurality of nodes. The operating system processes a designated application utilizing the plurality of nodes. During the processing, for each of the plurality of nodes, a determination is made of a quantity of times each memory location included within a shared-memory included within each of the plurality of nodes is accessed by each of the plurality of nodes.

Method and system in a distributed shared-memory data processing system for determining utilization of shared-memory included within nodes by a designated application

An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application level than kernel level. The implementation-independent kernel is involved only at very minimum level for a prologue to the exception handling routine. First a kernel extension registers an exception with the processor by storing the address of a pointer to a first-level interrupt handler; this address is stored in a location in kernel data storage, in non-paged memory. When an exception condition is reached, state is saved and the address location is checked to see if an exception has been registered. If so, the address is used to go to the first-level interrupt handler, which is at the kernel extension level. The first-level interrupt handler may access a second-level interrupt handler. Only the code which is used to save state and check to see if an exception is registered is in the kernel, and this part of the exception handling code is implementation-independent. i.e., the same for all implementations of this processor architecture.

Interupt vectoring for trace exception facility in computer systems

A method and apparatus for maintaining a list for threads which are awaiting their occurrence of event. First a thread is detected that desires to perform some type of action based upon the occurrence of an event. Thereafter, the value of an event list anchor is set to indicate that it is currently unavailable. Thereafter, the value of the event list anchor set equal to the identification of the second thread.

Method and system for using the event wait list anchor as a lock for

A method and system for altering data contained in a structure without requiring a lock to the structure itself. The method and apparatus retrieve a pointer to the structure from a location responsible for maintaining a pointer to the structure. The structure has a reference count for indicating processes that are currently using the data residing within the structure itself. The reference count is then atomically incremented and a new structure is obtained. The data contained in the structure, to be altered, is then copied to the new structure. The new structure also has a reference count for indicating processes that are currently using the data residing in the new structure. The reference count of the new structure is then set to indicate that a single process is accessing the new structure. Thereafter, the pointer in the responsible location for the structure, to be altered, is atomically replaced with a pointer to the new structure. The reference count of the new structure is then set to indicate that the single process is no longer accessing the new structure.

Method and apparatus for controlling access to data structures without

An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application-level than kernel level. The implementation-independent kernel is involved only at very minimum level for a prologue to the exception handling routine. First, a kernel extension registers an exception with the processor by storing the address of a pointer to a first-level interrupt handler; this address is stored in a location in kernel data storage, in non-paged memory. When an exception condition is reached, state is saved and the address location is checked to see if an exception has been registered. If so, the address is used to go to the first-level interrupt handler, which is at the kernel extension level. The first-level interrupt handler may access a second-level interrupt handler. Only the code which is used to save state and check to see if an exception is registered is in the kernel, and this part of the exception handling code is implementation-independent. i.e., the same for all implementations of this processor architecture.

Interrupt vectoring for instruction address breakpoint facility in

A method and apparatus for monitoring the execution of a procedure having multiple exit points without modifying the software via breakpoints. The starting address of the procedure is loaded into an Instruction Address Break Register (IABR). Upon execution of the starting address the IABR raises an exception. The processing of the exception is used to implement a counting routine and for loading the IABR with the address of the calling party via the Link Register. Upon execution of the address of the calling party, the IABR once again raises an exception. The processing of the second exception is used for stopping the counter and performing any related analysis.

Method and apparatus for improved instruction counting schemes

An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application-level than kernel level. The implementation-independent kernel is involved only at very minimum level for a prologue to the exception handling routine. First a kernel extension registers an exception with the processor by storing the address of a pointer to a first-level interrupt handler; this address is stored in a location in kernel data storage, in non-paged memory. When an exception condition is reached, state is saved and the address location is checked to see if an exception has been registered. If so, the address is used to go to the first-level interrupt handler, which is at the kernel extension level. The first-level interrupt handler may access a second-level interrupt handler. Only the code which is used to save state and check to see if an exception is registered is in the kernel, and this part of the exception handling code is implementation-independent. i.e., the same for all implementations of this processor architecture.

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Austin, TX, United States of America

James William Van Fleet