Intersil Americas Inc.

Zilog, Inc.

Zilog, Ind.

James William Leith

Gustavo James Mehas

Brandon Day

Matthew Burdet Harris

Bogdan M Duduman

Mark William Dickmann

Shying D Chen

A voltage regulator includes a voltage source for providing an input voltage. The regulator includes circuitry responsive to the input voltage for generating a regulated output voltage. The circuitry enables selection of one of internal linear voltage regulation or external linear voltage regulation for generating the regulated output voltage.

Configurable internal/external linear voltage regulator

A control circuit for a PWM switching power regulator including an error amplifier and an amplifier filter circuit. The error amplifier has a first input receiving a reference signal, a second input receiving an output sense signal, and an output providing a compensation signal used to control PWM switching. The amplifier filter circuit has an input receiving a ratio-metric tracking signal and an output providing the reference signal to the input of the error amplifier. The control circuit may include a resistive voltage divider for providing the tracking signal. The amplifier filter circuit may be implemented as a transconductance amplifier having an input receiving the tracking signal and an output coupled to a capacitor. The transconductance amplifier may have a relatively small current drive capacity and its output may have a relatively slow and weak response to changes of the tracking signal.

Voltage tracking reference for a power regulator

A pulse-width modulation (PWM) controller to supply power to electronic components using a phase lock loop (PLL) is presented. A PWM controller comprises an input node operable to receive a reference signal and a phase-locked loop (PLL). The PLL comprises an oscillator operable to receive an error-correction signal and to generate an oscillator signal having a frequency that is related to the error-correction signal, a phase-frequency detector (PFD) coupled to the oscillator and operable to receive the reference signal and to generate the error-correction signal based upon a phase difference between the reference signal and a feedback signal, and a suppression circuit coupled to the PFD and operable to periodically enable the PFD to generate the error-correction signal.

PWM controller with integrated PLL

A frequency programmable feed forward oscillator and triangular wave generator is disclosed having a first input for receiving an input voltage and a second input for receiving an input current. Circuitry within the device responsive to the input voltage scales the amplitude of a triangle wave form according to the provided input voltage and provides the scaled output voltage at a first output. In conjunction, the circuitry also generates a scaled PWM frequency responsive to the provided input current and provides this at a second output.

Frequency programmable feed-forward oscillator and triangle wave generator

Apparatus for providing over-current protection in a power converter device includes a first circuit for providing high-side sinking over-current protection for the power converter device responsive to a phase signal and a high-side over-current signal of the power converter device. A second circuit provides low-side sinking over-current protection for the power converter device responsive to the phase signal and the low-side over-current signal of the power converter device. Finally, a third circuit provides low-side sourcing over-current protection responsive to the phase signal, the low-side over-current protection signal and a power ground signal of the power converter device.

Apparatus for offset correcting high-side and low-side sinking/sourcing over-current protection

An apparatus for reducing surge currents during startup of a voltage regulator is disclosed that includes circuitry for maintaining a voltage at an FB pin of the voltage regulator substantially equivalent to an output voltage of the voltage regulator.

Startup via FB pin regulation

A PWM system that minimizes output ripple of a multiphase DC-DC converter which converts N input voltages including at least one dissimilar input voltage. The PWM system includes PWM waveform logic that generates N PWM signals including a PWM signal for each of the N input voltages, and PWM control logic that optimizes relative phases of the N PWM signals based on voltage levels of the N input voltages. Various circuits and/or methods are contemplated for optimizing phase, including, for example, centering pulses for each PWM cycle, distributing pulses based on predetermined optimal phase angles, determining input voltage levels and selecting predetermined optimal phase angles, generating phase signals employing predetermined phase angles, measuring input voltages and calculating optimal phase angles, and using PLL logic or the like to measure and equalize off-times between PWM pulses.

Multiphase DC-DC converter with reduced ripple

A startup circuit for a power converter including an amplifier circuit, a comparator, and startup logic. The power converter includes an error amplifier that compares an output sense signal with a startup reference signal and that provides a compensation signal. The amplifier circuit charges the startup reference signal to a predetermined reference level based on a second reference signal in response to a start signal. The comparator determines when the compensation signal reaches a predetermined ramp level and asserts a startup complete signal indicative thereof. The startup logic provides the start signal and provides an output enable signal in response to the startup complete signal. The output enable signal enables output switching to initiate normal regulation operation of the output voltage. In one embodiment, the predetermined ramp level is approximately the center voltage of a sawtooth regulation waveform used for PWM modulation.

Startup circuit for a DC-DC converter

A method of starting a DC&#x2014;DC converter into a precharged output voltage including generating a reference voltage having a linear relationship with the output voltage such that the reference voltage ranges between a minimum and maximum voltage level of a PWM triangular waveform as the output voltage ranges between zero and an input voltage level, and enabling output switching of the DC&#x2014;DC converter when the reference voltage is approximately equal to a compensation signal generated by an error amplifier comparing the reference voltage with a feedback signal representative of the output voltage. Generating a reference voltage may include applying a first current based on the input voltage through two resistors to develop the minimum and maximum voltage levels, applying the first current in one direction through a third resistor, and applying a second current based on the output voltage through the third resistor in the opposite direction.

Startup circuit for converter with pre-biased load

An IC including a margining control amplifier circuit, first and second offset pins, a margining control pin, select logic, and a mirror amplifier circuit. The margining control amplifier circuit drives current at an output to control voltage at an input based on a reference voltage. The first and second offset pins are provided to couple an external margining voltage divider. The margining control pin has at least two states including an up state and a down state. The select logic selectively switches the output of the margining control amplifier circuit between the first and second offset pins and selectively switches the input of the margining control amplifier circuit between the second and first offset pins based on a state of the margining control pin. The mirror amplifier circuit mirrors voltage across the first and second offset pins across a first margining resistor.

Precision margining circuitry

A sample and hold circuit uses an auto-zero feedback technique to cancel the DC level of the input signal and reference this signal to a new baseline. The circuit is based on an op-amp with two separate feedback loops. The first feedback loop is connected to the same op-amp input as the incoming signal and contains a capacitor to store charge from this signal during sample mode and set the output voltage during hold mode. The second feedback loop uses an auto-zero feedback technique and contains an integrator having a predetermined reference voltage, thereby allowing the DC level of the input signal to removed without the need for capacitors in the gain path of the circuit. This allows the sample and hold circuit to extract an embedded time varying signal from the input voltage. It can be configured for a high gain, high pass function, without the need for large electrolytic capacitors in the gain path, removing the problems associated with such capacitors. An exemplary embodiment of a three stage circuit for extracting an embedded signal lying in a frequency range, but having an amplitude much smaller than the DC component of the analog signal within which it is embedded. An initial low gain section acts as a buffer before the sample and hold section. Following the sample and hold section, the circuit employs a stage with a high gain high pass function also using auto-zero feedback. This again eliminates the large electrolytic capacitors usually placed the gain path that can not be implemented as part of a single integrated circuit. Besides eliminating the need for off-chip capacitors in the gain path, by using auto-zero feedback all sample and hold errors are referenced to the output of the sample and hold stage and are not amplified by the total system in a multi-stage configuration as the offset voltages of the amplifiers are not amplified.

Auto-zero feedback sample-hold system

A circuit for automatically driving a mechanical device at its resonance frequency is provided. To do so, the circuit detects non-resonance driving conditions of the mechanical device being coupled to and driven by such circuit. Based on such detection, the circuit generates a signal to drive the device at its resonance frequency.

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Seattle, WA, United States of America

James William Leith