General Electric Company

Lockheed Martin Corporation

James William Kretchmer

Dale M Brown

Kevin Sean Matocha

Peter Micah Sandvik

Richard J Saia

Stephen Daley Arthur

An-Ping Zhang

Jesse Berkley Tucker

Peter Almern Losee

Alexander Viktorovich Bolotnikov

William Andrew Hennessy

Mario Ghezzo

Gerald J Michon

Larry Burton Rowland

Tat-Sing P Chow

Vikram Bidare Krishnamurthy

Jeffrey Bernard Fedison

Edmund B Kaminsky

Ljubisa Dragoljub Stevanovic

Stacey Joy Kennerly

Zachary Matthew Stum

Kuna Venkat Satya Rama Kishore

Edmund Kaminsky, Jr

Dal Marius Brown

A semiconductor device is provided. The semiconductor device includes a semiconductor device layer having silicon carbide and having an upper surface and a lower surface. The semiconductor device also includes a heavily doped body region formed in the upper surface of the semiconductor device layer. The semiconductor device further includes a gate stack formed adjacent to and on top of the upper surface of the semiconductor device layer, wherein the gate stack is not formed adjacent to the heavily doped body region.

Semiconductor device layout and method for forming same

A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0&#xd7;10per cm.

Semiconductor device with junction termination extension

A high electron mobility transistor including: a GaN material system based heterostructure; a passivating nitride layer over the heterostructure and defining a plurality of openings; and a plurality of electrical contacts for the heterostructure and formed through the openings.

Method for making GaN-based high electron mobility transistor

A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Method of fabricating a MESFET with a sloped MESA structure

SiC metal semiconductor field-effect transistor

The invention is directed to a method for optical and electrical isolation between adjacent integrated devices. The method comprises the steps of forming at least one trench through an exposed surface of a semiconductor wafer by removing a portion of the semiconductor wafer material, forming an electrically insulating layer on the sidewalls and the bottom of the at least one trench, filling the at least one trench by conformally depositing an optically isolating material, and planarizing the semiconductor wafer surface by removing the portion of the optically isolating material above the exposed surface of the semiconductor wafer.

Integrated devices with optical and electrical isolation and method for making

A detection system for detecting gamma rays including a scintillator crystal for receiving at least one gamma ray and generating at least one ultraviolet ray and an avalanche photodiode for detecting the ultraviolet ray. The avalanche photodiode includes: a substrate having a first dopant; a first layer having a second dopant, positioned on top of the substrate; a passivation layer for providing electrical passivation on a surface of the avalanche photodiode; a phosphorous silicate glass layer for limiting mobile ion transport, positioned above of the first layer; and a pair of metal electrodes for providing an ohmic contact wherein a first electrode is positioned below the substrate and a second electrode is positioned above the first layer. The avalanche photodiode comprises a first sidewall and a second sidewall forming a sloped mesa shape.

Detection system including avalanche photodiode for use in harsh environments

An aspect of the present invention is directed to an avalanche photodiode (APD) device for use in oil well drilling applications in harsh, down-hole environments where shock levels are near 250 gravitational acceleration (G) and/or temperatures approach or exceed 150&#xb0; C. Another aspect of the present invention is directed to an APD device fabricated using SiC materials. Another aspect of the present invention is directed to an APD device fabricated using GaN materials. According to an embodiment of the present invention, an avalanche photodiode for detecting ultraviolet photons comprises a substrate having a first dopant; a first layer having the first dopant, positioned on top of the substrate; a second layer having a second dopant, positioned on top of the first layer; a third layer having a second dopant, positioned on top of the second layer; a passivation layer for providing electrical passivation on a surface of the avalanche photodiode; a phosphorous silicate glass layer for limiting mobile ion transport, positioned on top of the third layer; and a pair of metal electrodes for providing an ohmic contact wherein a first electrode is positioned below the substrate and a second electrode is positioned above the third layer; wherein the avalanche photodiode comprises a first sidewall and a second sidewall forming a sloped mesa shape; and wherein the avalanche photodiode operates in an environment comprising a temperature approximately equal to 150 degrees Celsius.

Avalanche photodiode for use in harsh environments

A flame sensor for combustion flame temperature determination comprises elongated extensions that are positioned with parallel interdigitated longitudinal axis with respect to one another. An optical spectrometer comprises the sensor and a system comprises the sensor. A method for combustion flame temperature determination comprises obtaining a first photodiode signal and a second photodiode signal by using photodiode devices comprising photodiodes with elongated extending interdigitated digits. A method of fabricating a flame sensor for combustion flame temperature determination, comprises forming first and second photodiodes with elongated extending interdigitated digits.

Interdigitated flame sensor, system and method

A depletion mode MOSFET and resistor are fabricated as a silicon carbide (SiC) integrated circuit (IC). The SiC IC includes a first SiC layer doped to a first conductivity type and a second SiC layer overlaid on the first SiC layer and doped to a second conductivity type. The second SiC layer includes at least four more heavily doped regions of the second conductivity type, with two of such regions comprising MOSFET source and drain electrodes and two other of such regions comprising resistor electrodes. The second SiC layer includes an isolation trench between the MOSFET electrodes and the resistor electrodes. At least two electrically conductive contacts are provided as MOSFET electrode contacts, each being positioned over at least a portion of a respective MOSFET electrode and two other electrically conductive contacts are provided as resistor electrode contacts, each being positioned over at least a portion of a respective resistor electrode. An oxide layer extends over the second SiC layer with at least a portion of the oxide layer positioned between the MOSFET electrode contacts. A MOSFET gate electrode is positioned over the oxide layer, and coupling means are provided for electrically coupling one of the source, drain, and gate electrodes to one of the resistor electrodes.

Silicon carbide integrated circuits

A semiconductor device includes a semiconductor substrate having an epitaxial layer surface opposite a drain contact surface; a semiconductor layer adjacent to the epitaxial layer surface of the substrate, the semiconductor layer including material of a first conductivity type; a patterned refractory dielectric layer adjacent to the semiconductor layer; a base region of implanted ions in the semiconductor layer, the base region being of a second conductivity type; a source region of implanted ions in the base region, the source region being of the first conductivity type; a gate insulator layer adjacent to at least a portion of the source and base regions of the semiconductor layer; and a gate electrode over a portion of the gate insulator layer, adjacent to and in physical contact with an outer edge of the patterned refractory dielectric layer, and over at least a portion of the base region between the source region and the patterned refractory dielectric layer.

Self-aligned transistor device including a patterned refracting

A method for fabricating a semiconductor device includes patterning a refractory dielectric layer over a semiconductor layer of a first conductivity type; conformally depositing a first spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the first spacer layer to leave a first spacer adjacent to an edge of the patterned refractory dielectric layer; implanting ions of a second conductivity type to form a base region in the semiconductor layer; conformally depositing a second spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the second spacer layer to leave a second spacer adjacent to an edge of the first spacer; implanting ions of the first conductivity type to form a source region in the base region; removing the first and second spacers; applying a gate insulator layer over at least a portion of the semiconductor layer; conformally depositing a gate electrode layer over the gate insulator layer and the semiconductor layer; and patterning the gate electrode layer to form a gate electrode portion adjacent to an edge of the patterned refractory dielectric layer. Preferably the step of conformally depositing the gate electrode layer includes depositing an electrically conductive layer having the same thickness as a combined width of the first and second spacers. In one embodiment the semiconductor layer includes silicon carbide, the patterned refractory dielectric layer includes silicon dioxide, the spacers include silicon nitride, and the gate electrode layer includes polysilicon.

Method of fabricating a self-aligned DMOS transistor device using SiC

A depletion mode MOSFET and resistor are fabricated as a silicon carbide (SiC) integrated circuit (IC). The SiC IC includes a first SiC layer doped to a first conductivity type and a second SiC layer overlaid on the first SiC layer and doped to a second conductivity type. The second SiC layer includes at least four more heavily doped regions of the second conductivity type, with two of such regions comprising MOSFET source and drain electrodes and two other of such regions comprising resistor electrodes. The second SiC layer includes an isolation trench between the MOSFET electrodes and the resistor electrodes. At least two electrically conductive contacts are provided as MOSFET electrode contacts, each being positioned over at least a portion of a respective MOSFET electrode and two other electrically conductive contacts are provided as resistor electrode contacts, each being positioned over at least a portion of a respective resistor electrode. An oxide layer extends over the second SiC layer with at least a portion of the oxide layer positioned between the MOSFET electrode contacts. A MOSFET gate electrode is positioned over the oxide layer, and coupling means are provided for electrically couping one of the source, drain, and gate electrodes to one of the resistor electrodes.

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Ballston Spa, NY, United States of America

James William Kretchmer