International Business Machines Corporation

Other

James Warren Wilson

Robert David Sebesta

Scott Preston Moore

John Steven Kresge

Robin A Susko

John Joseph Konrad

Eric H Laine

Voya Rista Markovich

Natalie Barbara Feilchenfeld

William E Wilson

Gerald Walter Jones

Ross William Keesler

Ronald P Nowak

Konstantinos I Papathomas

Thomas R Miller

William John Rudik

Michael Wozniak

Jeffrey Alan Knight

Timothy Leroy Wells

Jeffrey McKeveny

Allen Frederick Moring

Stephen Wesley MacQuarrie

Robert Douglas Edwards

Stephen R Engle

Kenneth J Lubert

Curtis L Miller

Wayne R Storr

Dorothy E Wilson

John A Welsh

Michael Robert Weber

Russell Thomas White, Jr

Kim Joseph Blackwell

Jeffrey Alan Zimmerman

Charles A Joseph

Heinke Marcello

Francis J Olshefski

Brenda D Frey

Alan W Chase

Douglas E Chrzanowski

An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10&#x2013;17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel-gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on-opposite sides of a substrate.

Variable thickness pads on a substrate surface

Embedded flush circuitry features are provided by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a layer of dielectric material.

Structure having laser ablated features and method of fabricating

An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10-17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel-gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on opposite sides of a substrate.

Embedded flush circuitry features are provided by depositing a conductive seed layer on the front side of a sacrificial carrier; plating a layer of conductive metal onto the seed layer and personalizing circuitry features. The front side of the carrier film is embedded into a dielectric material and the sacrificial carrier film is removed.

Structure having embedded flush circuitry features and method of fabricating

A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.

Process of fabricating a circuitized structure

Embedded flush circuitry features are fabricated by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a later of dielectric material.

A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.

Fine pitch circuitization with filled plated through holes

CTE differentials between chips and organic dielectric carriers, boards or other substrates to which the chips are attached are accommodated with a layer of a thermoplastic material, preferably a thermotropic polymer whose physical properties can be altered by extrusion or other physical processes, such as liquid crystalline polyesters, that modifies the CTE of at least one component of the package and thereby reduces CTE differentials. The material may be applied to the entire surface of a chip carrier, printed circuit or other substrate, or form an interior layer of a multi-layered structure. It may also be applied to selected regions or areas on the surface of a carrier or other substrate where adjustment is required.

Methods and apparatus for balancing differences in thermal expansion in electronic packaging

A process and apparatus are described for wire bonding circuit pads of large scale integrated design. The bonding process employs a capillary tool that applies heat and pressure to the wires in order to bond them to the circuit pad. The circuit pad is supported upon a closed woven, fiberglass mesh, which supports the circuit pad during the bonding process.

Wire bonding method and apparatus

Printed circuit boards, cards and chip carriers are fabricated by treating an already circuitized substrate with a swelling agent, then treating the circuitized substrate with a composition containing an alkaline permanganate, a chromate and/or chlorite and then applying a metal layer to coat the circuitized portion of the substrate.

Process for reducing extraneous metal plating

The present invention provides an organic chip carrier particularly useful with flip chips. The chip carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about 2.0 mil or less, preferably about 1.0 mil or less, and more preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.

Polytetrafluoroethylene thin film chip carrier

CTE differentials between chips and organic dielectric carriers, boards or other substrates to which the chips are attached are accommodated with a layer of a thermoplastic material, preferably a thermotropic polymer whose physical properties can be altered by extrusion or other physical processes, such as liquid crystalline polyesters, that modifies the thermal expansion of at least one component of the package and thereby reduces CTE differentials. The material may be applied to the entire surface of a chip carrier, printed circuit or other substrate, or form an interior layer of a multi-layered structure. It may also be applied to selected regions or areas on the surface of a carrier or other substrate where adjustment is required.

Integrated circuit chip device having balanced thermal expansion

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Vestal, NY, United States of America

James Warren Wilson