International Business Machines Corporation

James Warren Dieffenderfer

Peter Michael Kogge

Paul Amba Wilkinson

Nicholas Jerome Schoonover

Thomas Norman Barker

Michael C Dapp

Vincent John Smoral

Richard Edward Nier

David B Rolfe

Billy J Knowles

Clive Allan Collins

Donald Michael Lesmeister

Robert Reist Richardson

Eric Eugene Retter

Richard Ernest Miles

James Robert Stupp

David Christopher Kuchinski

Donald George Grice

Donald G Grice

James Norris Dieffenderfer

David Christoper Kuchinski

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD, and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64, or 128,000 processors. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as work-station or supercomputer.

SIMD/MIMD processing synchronization

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD.

SIMD/MIMD array processor with vector processing

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processor memory elements on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. The architecture uses all the pins for networking. Each chip has eight 16 bit processors, and eight respective 32K memories. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. The scalable chip has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. A fully distributed programmable router is provided by the processing memory elements that form a node. There is program compatibility for the fully scalable system.

APAP I/O programmable router

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

Fully distributed processing memory element

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD.

Partitioning of processing elements in a SIMD/MIMD array processor

Array processor with asynchronous availability of a next SIMD instruction

A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Advanced parallel array processor (APAP)

Array processors are made by assembling individual microcomputer elements into an array. Larger arrays are called massively parallel processors. Some can operate in SIMD, while others can operate in MIMD, or SIMD and MIMD in special configurations. In a SIMD array of processors, there is a need to partition the processors into groups related to the type of problem they contain. When the grouping is the result of a computation within the processing element, it is desirable that each processing element be capable of assigning itself to a group, or maybe several groups. This disclosure describes a means of assigning processing elements to groups as an array function conducted in parallel by all active processing elements in the array, and then using grouping to select certain processing elements for a computation that is unique to the group.

Array processor having grouping of SIMD pickets

Multiprocessor parallel computing systems and a byte serial SIMD processor parallel architecture is used for parallel array processing with a simplified architecture adaptable to chip implementation in an air cooled environment. The array provided is an N dimensional array of byte wide processing units each coupled with an adequate segment of byte wide memory and control logic. A partitionable section of the array containing several processing units are contained on a silicon chip arranged with 'Picket's, an element of the processing array preferably consisting of combined processing element with a local memory for processing bit parallel bytes of information in a clock cycle. A Picket Processor system (or Subsystem) comprises an array of pickets, a communication network, an I/O system, and a SIMD controller consisting of a microprocessor, a canned routine processor, and a microcontroller that runs the array. The Picket Architecture for SIMD includes set associative processing, parallel numerically intensive processing, with physical array processing similar to image processing, a military picket line analogy fits quite well. Pickets, having a bit parallel processing element, with local memory coupled to the processing element for the parallel processing of information in an associative way where each picket is adapted to perform one element of the associative process. We have provided a way for horizontal association with each picket. The memory of the picket units is arranged in an array. The array of pickets thus arranged comprises a set associative memory. The set associative parallel processing system on a single chip permits a smaller set of `data` out of a larger set to be brought out of memory where an associative operation can be performed on it. This associative operation, typically an exact compare, is performed on the whole set of data in parallel, utilizing the Picket's memory and execution unit.

Associative parallel processing system

A parallel array computer provides an array of processor memory elements interconnected for transfer of data and instructions between processor memory elements. Each of the processing elements has a processor coupled with a local memory. An array controller is provided for controlling the operation of the array of processor memory elements. Each of the processor memory elements has a plurality of local autonomous operating modes and is adapted to interpret instructions from the array controller within the processor memory element.

Picket autonomy on a SIMD machine

A floating point system and method according to a format that includes a sign bit, an exponent part having a plurality of bits, and a fraction part having a plurality of multi-bit blocks, wherein floating point operation is based on block shifts of the fraction part, with each shift of one block associated with an increment or decrement of the exponent part by one count. This format illustrated is implemented as a format suitable for the accuracy greater than the IEEE 32-bit floating-point format, and is intended to be implemented in machines having byte-wide (8 bit) data streams. The preferred format consists of a sign bit, 7 exponent bits and 4 fraction bytes of eight bits for a total of 40 bits. This format and implementation allows floating-point commands to be executed in a fixed small number of cycles, thus advancing the capabilities of doing floating-point arithmetic on a SIMD machine. The floating-point implementation is adaptable to multiprocessor parallel array processor computing systems and for parallel array processing with a simplified architecture adaptable to chip implementation. The array provided is an N dimensional array of byte-wide processing units each coupled with an adequate segment of byte-wide memory and control logic. A partitionable section of the array containing several processing units is contained on a silicon chip arranged with eight elements of the processing array each preferably consisting of combined processing element with a local memory for processing bit parallel bytes of information in a clock cycle. A processor system (or subsystem) comprises an array of pickets, a communication network, an 1/0 system, and a SIMD controller consisting of a microprocessor, a canned-routine processor, and a microcontroller that runs the array.

Floating point for simid array machine

A conventional SIMD processor array architecture's functions are amplified by a SIMIMD architecture where more programmable flexibility would be useful. Decision making in general and specifically classification where decision trees are common, is a problem eased by SIMIMD. A SIMD array processor having a plurality of pickets in SIMIMD mode allows each picket to occasionally execute data-dependent instructions that are different from the instructions in other pickets to greatly improve execution efficiency in decision making areas. Every element in A SIMD array of processors receives a stream of commands from the array controller. Here several mechanisms allow an array machine with individual processing elements, called pickets, to interpret some of the SIMD commands in their own unique way, giving each picket a degree of local autonomy. A resulting capability allows the pickets to execute instructions in a mode called SIMIMD. Another resulting capability boosts the performance of executing floating-point instructions significantly. Yet another capability provides for GROUPING of pickets in various useful ways such that a combination of groups can be executing SIMD instructions while others are DOZING. There are other resulting capabilities. The SIMD machine is used alone or as part of multiprocessor parallel array processor computing systems and for parallel array processing with a simplified architecture adaptable to chip implementation in an air-cooled environment. The array provided is an N dimensional array of byte-wide processing units each coupled with an adequate segment of byte-wide memory and control logic. A partitionable section of the array containing several processing units are contained on a silicon chip arranged with 'pickets', elements of the processing array, each preferably consisting of combined processing element with a local memory for processing bit parallel bytes of information in a clock cycle.

SIMIMD array processing system

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAWM processing while incorporating processing elements on a single chip, with nodes connected in an n-dimensional modified non-binary hypercube. In a 4-dimensional modified non-binary hypercube embodiment, each node includes either processor memory elements on a single chip, each processor memory element having its own associated processing element, significant memory, and I/O, with each processor memory element supporting an external port. Pairs of ports are associated with each dimension, labeled X, Y, W, and Z. Eight nodes are connected in the X dimension to form a ring. Corresponding nodes from eight such rings are connected into rings in the Y dimension to form an 8.times.8 array of nodes, referred to as a cluster. Corresponding nodes of eight clusters are connected into ring (64 rings) in the Z dimension, forming an 8.times.8.times.8 array of nodes referred to as a 'cluster ring'. Corresponding nodes of eight cluster rings are connected into rings in the W dimension.

N-dimensional modified hypercube

A controller for a SIMD processor array that can execute instructions within each processing element is described. This three stage hierarchical controller executes instructions at the function, routine, and micro-level, to maximize the effectiveness of processing within the array elements themselves. The routine sequencer is hardwired to perform looping and flow control operations using DO/WHILE, IF/THEN/ELSE, and GO-SUB constructs. A pipeline is provided to maintain a steady flow of commands to the array, and means is provided to monitor command execution progress and to provide feedback of progress to the stages of the controller.

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Owego, NY, United States of America

James Warren Dieffenderfer