Vlsi Technology, Inc.

James Ward

Richard W Ulmer

Marty L Long

Laura Elisabeth Simmons

An input/output (I/O) controller uses a single transceiver to service multiple I/O ports in a small computer system, such as an IBM PS/2 computer. Arbitration logic controls the access of the ports to the transceiver, and once the arbitration logic directs one of the ports to the transceiver, all other I/O devices are locked out until the transfer to or from the current I/O device is complete. Once the current transfer is complete, the arbitration logic then goes back to arbitrating, looking for the next I/O device that needs service. The associated circuitry to implement the arbitration and control logic is much smaller than the circuitry required for an additional transceiver, resulting in a lower system cost.

Input/output controller circuit using a single transceiver to serve

A combination keyboard and keyboard/mouse controller system is capable of use with different types of personal computers, using either a keyboard input alone or a keyboard/mouse combination. The controller is configured with a hardware transceiver in it, and includes interconnections between an accumulator and a microsequencer portion and a transceiver for effecting the transfer of data to and from the computer and the keyboard or keyboard/mouse combination. The configuration of the controller circuitry is such that logic gates and multiplex transmission gates are employed between various ones of the input terminals to which signals are applied, and output terminals to which signals are provided. These gates interconnect at least some of these terminals in different combinations in different modes of operation of the controller system, depending upon whether a computer uses a keyboard alone as a data input device or is operated with a combination of a keyboard and mouse. The switching from one of these modes of operation to the other is effected by means of a binary control signal applied on a common terminal to the controller circuit.

Universal keyboard and keyboard/spatial input device controller

A low-skew CMOS clock divider circuit for providing tracking of the divide-by-one and divide-by-two output signals obtained from a source of master clock pulses is fabricated using two matched flip-flops externally wired as divide-by-two devices. Coincidence gates are coupled with the outputs of the flip-flops to produce the desired divide-by-one and divide-by-two output signals in a manner such that the signals in each path pass through substantially identical circuit components, Thus, any delays encountered are the same in both circuit paths. In this manner, skew between the edges of the divide-by-two and divide-by-one clock signals is significantly reduced.

Low skew CMOS clock divider

A logic level shifter characterized by a first inverting stage which shifts an input signal downwardly to a lower level, and a second inverting stage which shifts the lower level upwardly to an output signal level which is greater than the input signal level. Feedback from the output is used to virtually eliminate static current drain when the input logic level is 0. The method of the invention involves downwardly shifting an input range of voltages to a lower range of voltages, and then upwardly shifting the lower range of voltages to an output range of voltages which is greater than the input range of voltages. There is preferably a first inversion in the downward shift and a second inversion in the upward shift. A sensing step senses the output voltage to reduce the static current consumed by the process.

Logic level shifter for 3 volt CMOS to 5 volt CMOS or TTL

A CMOS drive circuit an integrated circuit bonding pad is controlled by a pre-driver signals to change the potential on the output pad in accordance with these signals. Undesirable interference (emi) problems are eliminated or significantly reduced by slowing the ramp of change of the signal appearing on the output bonding pad when it changes from a high or positive binary state to a lower, relatively negative binary state. This is effected by splitting the output NMOS transistor of the CMOS output driver into two parallel connected, relatively small-sized transistor. Each of these transistors is driven from the signal input terminal through a relatively low current source which causes the gate capacitance to be slowly charged.

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Gilbert, AZ, United States of America

James Ward