International Business Machines Corporation

Microsoft Technology Licensing, LLC

James Walter Rymarczyk

Thomas James Heller, Jr

Michael Ignatowski

Richard I Baum

Bernard S Meyerson

John Stephen Liptay

Charles H Brotman

Renato John Recio

William Joseph Armstrong

Richard Louis Arndt

Jacobo A Vargas

Stanley E Stone

Jeffrey F Hughes

A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.

Multiple-core processor supporting multiple instruction set architectures

Multiple instruction set architectures are supported in a system that provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). A processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. A hypervisor controls operation of the cores, locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. The ISA may be specified by a particular operating system and/or application program requirements.

An audio application program is isolated from an Internet application program in a cell phone system having a processor. An operating system program, a partition manager process and the audio and Internet application programs are stored in a computer readable memory of the cell phone. The method includes executing the partition manager process, the audio application program and the Internet application program by the cell phone system processor. Executing the partition manager process includes the partition manager process controlling the audio application program executing to be associated with a first executing instance of the cell phone operating system and the Internet application program executing to be associated with a second executing instance of the cell phone operating system, so that the audio application program is isolated from the Internet application program.

Method, apparatus and computer program product for cell phone security

A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.

System and computer program product for dynamically managing power in microprocessor chips according to present processing demands

A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller. The second level controller uses the mode bits to determine which nodes must receive any given transaction that is received by the second level controller. Logical partitions are mapped to allowable physical processors. Cache coherence regions which encompass subsets of the total number of processors and caches in the system are chosen for their physical proximity. A distinct cache coherency region can be defined for each partition using a a hypervisor.

Multiprocessor system with dynamic cache coherency regions

Method for dynamically managing power in microprocessor chips according to present processing demands

A large number of processing elements (e.g. 4096) are interconnected by means of a high bandwidth switch. Each processing element includes one or more general purpose microprocessors, a local memory and a DMA controller that sends and receives messages through the switch without requiring processor intervention. The switch that connects the processing elements is hierarchical and comprises a network of clusters. Sixty-four processing elements can be combined to form a cluster and sixty four clusters can be linked by way of a Banyan network. Messages are routed through the switch in the form of packets which includes a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the swithc reverses the source and destination field and returns the packet to the sender with an error flag. If the packet is misrouted to a functional processing element, the processing element corrects the error and retransmits the packet through the switch over a different path. In one embodiment, each processing element can be provided with a hardward accelerator for database functions. In this embodiment, the multiprocessor of the present invention can be employed as a coprocessor to a 370 host and used to perform database functions.

Multiprocessing packet switching connection system having provision for

A large number of processing elements (e.g. 4096) are interconnected by means of a high bandwidth switch. Each processing element includes one or more general purpose microprocessors, a local memory and a DMA controller that sends and receives messages through the switch without requiring processor intervention. The switch that connects the processing elements is hierarchical and comprises a network of clusters. Sixty-four processing elements can be combined to form a cluster and sixty four clusters can be linked by way of a Banyan network. Messages are routed through the switch in the form of packets which include a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the switch reverses the source and destination field and returns the packet to the sender with an error flag. If the packet is misrouted to a functional processing element, the processing element corrects the error and retransmits the packet through the switch over a different path. In one embodiment, each processing element can be provided with a hardware accelerator for database functions. In this embodiment, the multiprocessor of the present invention can be employed as a coprocessor to a 370 host and used to perform database functions.

In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.

Multi-instruction stream branch processing mechanism

Operand controls are provided in an I-unit using address operand pairs (AOPs), each pair consisting of a request register and a buffer register. When handling variable field length (VFL) instructions with source (SRC) and destination (DST) operand addresses, two AOPs are generally assigned to receive different parts of the first subline (e.g. doubleword) of the SRC operand; this is called a duplicate fetch and is used with any size VFL operand. Efficiency is improved for the special case in which the DST operand has all of its bytes confined to a single subline in main storage by detecting the special case and inhibiting a duplicate fetch signal to the I-unit controls which assign duplicate AOPs to an instruction. The SRC operand may have more than one subline but the alignment controls force all source operand bytes into a single subline for the special case. When the duplicate fetch signal is suppressed, only one AOP is assigned by the controls to the first subline fetch for the SRC operand.

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Austin, TX, United States of America

James Walter Rymarczyk