Microchip Technology Inc.

Freescale Semiconductor,inc.

James Walls

Paul Fest

Mel Hymas

Sonu Daryanani

Bomy A Chen

Greg Stom

Sajid Kabeer

Luc Reboulet

A memory cell, e.g., a flash memory cell, includes a substrate, a flat-topped floating gate formed over the substrate, and a flat-topped oxide region formed over the flat-topped floating gate. The flat-topped floating gate may have a sidewall with a generally concave shape that defines an acute angle at a top corner of the floating gate, which may improve a program or erase efficiency of the memory cell. The flat-topped floating gate and overlying oxide region may be formed with without a floating gate thermal oxidation that forms a conventional 'football oxide.' A word line and a separate erase gate may be formed over the floating gate and oxide region. The erase gate may overlap the floating gate by a substantially greater distance than the word line overlaps the floating gate, which may allow the program and erase coupling to the floating gate to be optimized independently.

Memory cell with a flat-topped floating gate structure

A method of forming a memory cell, e.g., flash memory cell, may include (a) depositing polysilicon over a substrate, (b) depositing a mask over the polysilicon, (c) etching an opening in the mask to expose a surface of the polysilicon, (d) growing a floating gate oxide at the exposed polysilicon surface, (e) depositing additional oxide above the floating gate oxide, such that the floating gate oxide and additional oxide collectively define an oxide cap, (f) removing mask material adjacent the oxide cap, (g) etching away portions of the polysilicon uncovered by the oxide cap, wherein a remaining portion of the polysilicon defines a floating gate, and (h) depositing a spacer layer over the oxide cap and floating gate. The spacer layer may includes a shielding region aligned over at least one upwardly-pointing tip region of the floating gate, which helps protect such tip region(s) from a subsequent source implant process.

Memory cell with oxide cap and spacer layer for protecting a floating gate from a source implant

An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

Flash memory cell with dual erase modes for increased cell endurance

A method is provided for forming an integrated circuit memory cell, e.g., flash memory cell. A pair of spaced-apart floating gate structures may be formed over a substrate. A non-conformal spacer layer may be formed over the structure, and may include spacer sidewall regions laterally adjacent the floating gate sidewalls. A source implant may be performed, e.g., via HVII, to define a source implant region in the substrate. The spacer sidewall region substantially prevents penetration of source implant material, such that the source implant region is self-aligned by the spacer sidewall region. The source implant material diffuses laterally to extend partially under the floating gate. Using the non-conformal spacer layer, including the spacer sidewall regions, may (a) protect the upper corner, or 'tip' of the floating gate from rounding and (b) provide lateral control of the source junction edge location under each floating gate.

Floating gate spacer for controlling a source region formation in a memory cell

A memory cell, e.g., a flash memory cell, includes a substrate, a floating gate formed over the substrate, and a word line and an erase gate formed over the floating gate. The word line overlaps the floating gate by a first lateral overlap distance, and the erase gate overlaps the floating gate by a second lateral overlap distance that is substantially greater than the first lateral distance. This configuration allows the program and erase coupling to the floating gate to be optimized independently, e.g., to decrease or minimize the program current and/or increase or maximize the erase current for the cell.

Memory cell with asymmetric word line and erase gate for decoupled program erase performance

A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing an etch to remove portions of the bottom electrode layer to form at least one upwardly-pointing bottom electrode region above the bottom electrode connections, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.

Resistive memory cell with sloped bottom electrode

A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed.

Resistive memory cell having a reduced conductive path area

A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. The first memory element defines a first conductive filament/vacancy chain path from the first portion of the bottom electrode pointed tip region to the first top electrode via the first electrolyte region, and second memory element defines a second conductive filament/vacancy chain path from the second portion of the bottom electrode pointed tip region to the second top electrode via the second electrolyte region.

Resistive memory cell having a single bottom electrode and two top electrodes

A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include: forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines at least one sloped surface, forming an oxidation layer on each sloped surface of the remaining bottom electrode layer, performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.

Resistive memory cell with bottom electrode having a sloped side wall

A resistive memory cell, e.g., CBRAM or ReRAM cell, may include a top electrode an a trench-shaped bottom electrode structure defining a bottom electrode connection and a sidewall extending from a first sidewall region adjacent the bottom electrode connection to a tip region defining a tip surface facing generally away from the bottom electrode connection, and wherein the tip surface facing away from the bottom electrode connection has a tip thickness that is less than a thickness of the first sidewall region adjacent the bottom electrode connection. An electrolyte switching region is arranged between the top electrode and the bottom electrode sidewall tip region to provide a path for the formation of a conductive filament or vacancy chain from the bottom electrode sidewall tip surface of the top electrode, via the electrolyte switching region, when a voltage bias is applied to the resistive memory cell.

Resistive memory cell with trench-shaped bottom electrode

A resistive memory cell, e.g., a CBRAM or ReRAM cell, may include a top electrode, a bottom electrode having an elongated trench shape defining a pair of spaced-apart bottom electrode sidewalls, and an electrolyte switching region arranged between the top electrode and at least one of the bottom electrode sidewalls to provide a path for the formation of a conductive filament or vacancy chain from the at least one bottom electrode sidewall to the top electrode when a voltage bias is applied to the cell. In addition, a memory may include an array of resistive memory cells including a top electrode structure, a plurality of trench-style bottom electrodes extending in first direction, and a plurality of inverted-trench-style electrolyte switching regions extending perpendicular to the trench-style bottom electrodes to define a two-dimensional array of spaced-apart contact areas between the electrolyte switching regions and the bottom electrodes.

An electrical component () having an inductor includes: (a) a first substrate () comprising at least one first electrically conductive layer (); (b) one or more second substrates () comprising at least one second electrically conductive layer (); and (c) one or more electrical interconnections () electrically coupling the at least one first electrically conductive layer and the at least one second electrically conductive layer, wherein the one or more first electrically conductive layers, the one or more second electrically conductive layers and the one or more electrical interconnections are electrically coupled together to form the inductor ().

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Mesa, AZ, United States of America

James Walls