Intel Corporation

Other

James W Tschanz

Vivek K De

Muhammad M Khellah

Siva G Narendra

Jaydeep P Kulkarni

Carlos Alfonso Tokunaga

Yibin Ye

Stephen H Tang

Dinesh Somasekhar

Charles Augustine

Shih-Lien L Lu

Arijit Raychowdhury

Shigeki Tomishima

Tanay Karnik

Christopher B Wilkerson

Nasser A Kurd

Wei Wu

Javed Sabir Barkatullah

Ming Lei Zhang

Greg F Taylor

Subramaniam M Maiyuran

Ram K Krishnamurthy

Yih Wang

Fatih Hamzaoglu

Sriram R Vangal

Willem M Beltman

Helia A Naeimi

Nitin Y Borkar

Pratik A Patel

Brian S Doyle

Stefan Rusu

Donald S Gardner

Charles C Kuo

Robert F Kwasnick

Gerhard Schrom

Shekhar Yeshwant Borkar

Rahul Khanna

Peter Hazucha

Ali Keshavarzi

David L Kencke

Daniel Nemiroff

Joseph Shor

Scott H Robinson

Michael E Deisher

Patrick Koeberl

Keith A Bowman

Bibiche M Geuskens

Nam Sung Kim

Chris Wilkerson

Victor Zia

Randy J Aksamit

Minki Cho

Badarinath N Kommandur

Janice C Lee

Maged Ghoneima

Dejan Markovic

Amit R Trivedi

Rinkle Jain

Mircea R Stan

Stephen Kim

Pascal A Meinerzhagen

Georgios Panagopoulos

Peter Caputa

Yi-Chun Shih

Yehea I Ismail

Miguel Bautista Gabriel

Muhammed M Khellah

Yiben Ye

Kaushik Mazumdar

Manoj Sachdev

Roksana Golizadeh Mojarad

Liqiong Wei

Ali Taha

Pascal Meinerzhagen

Cyrille Dray

Sandip Kundu

Subhasish Mitra

Suyoung Bang

Nathaniel August

Thomas E Walsh

Howard A Wilson

Kah Meng Yeem

Daniel S Klowden

Pulkit Jain

Yaxin Shui

William Zand

Suriya Kumar

Shih-Lien L Liu

Yibin Yee

Xin Kang

Rangharajan Venkatesan

Joseph F Ryan

Miguel Mario Bautista Gabriel

An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.

Detecting laser-injected faults

A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

Circuits and methods for supply voltage detection and timing monitoring

Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.

Methods and apparatus to optimize a guard band of a hardware resource

Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

Dual loop digital low drop regulator and current sharing control apparatus for distributable voltage regulators

A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.

Circuits and methods for voltage detection in integrated circuits

Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

Bitcell state retention

Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.

Graphics processor sub-domain voltage regulation

An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Magnetic storage cell memory with back hop-prevention

An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.

Retention minimum voltage determination techniques

An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.

Adaptive voltage system for aging guard-band reduction

Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Sequential circuit with error detection

Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.

Apparatus for charge recovery during low power mode

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Hillsboro, OR, United States of America

James W Tschanz