Peregrine Semiconductor Corporation

James W Swonger

Mark L Burgener

Ronald Eugene Reedy

Buddhika Abesingha

Merlin Green

Tero Tapio Ranta

Dan William Nobbe

Robert J Broughton

R Mark Englekirk

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.

Integrated level shifter circuit

Level shifter

A multi-stage device for boosting an input voltage is discussed. Each stage of the device comprises a stage of a ring oscillator and a charge pump. An oscillating signal, generated by the ring oscillator within the device, drives the charge pump in each stage of the device. The charge pumps of the stages are serially connected. A final stage of the multi-stage device is adapted to provide voltage to a load circuit. The multi-stage device is applicable for generation of different bias voltages from one or more source voltages.

High voltage ring pump with inverter stages and voltage boosting stages

A power detection system is disclosed that determines a power level of a transmission signal. The power detection system includes an adjustable comparator circuit, an algorithmic state machine, and an output node. The adjustable comparator circuit receives the transmission signal and provides an adjusted transmission signal, and further compares the adjusted transmission signal to a reference signal. The algorithmic state machine iteratively adjusts the adjustable comparator circuit until the adjusted transmission signal is substantially close to the reference signal. The output node is coupled to the algorithmic state machine and provides an output signal that is responsive to the power level of the transmission signal and to the reference signal.

Systems and methods for providing improved power performance in wireless communication systems

Growing community of inventors

Cocoa, FL, United States of America

James W Swonger