Cray Research, Inc.

James W Sundet

Steven J Dean

Eugene N Reshanov

Eric J Mueller

Roger G Brown

Amy Bower

James W Luther

Robert A Moe

Computer cabinet

A fault tolerant network for a plurality of computers includes a system for controlling access to shared peripherals. Access to the shared peripherals is coordinated among the computers by means of communication through a semaphore box. Each computer connects to the semaphore box via a channel. The semaphore box is comprised of two major sections: a semaphore section and an I/O section. The semaphore section contains two sets of semaphores: a first set comprising reservation semaphores for the shared peripherals; and a second set comprising heartbeat semaphores for the sharing computers. The first set is used to reserve a particular peripheral for a particular computer and indicate the source of the reservation; the second set provides a 'heartbeat' to prevent reservation semaphores from being set indefinitely in the event communication with a particular computer is lost.

Fault tolerant networking architecture

A solid state storage device is disclosed. The storage sections of the device are divided into two groups, with each group including at least one, and as many as four storage sections. A port is provided for delivering words to and receiving words from the sections. A data path between the port and the device is two words wide, with one word received from or delivered to each group. Each section includes a word storage register, with the registers of different sections in the same group being connected in a series fashion to provide a one word data path between the storage sections. Words stored or retrieved from a section are passed through its respective register. In a write operation, words to be stored are transmitted serially from register to register and captured by all sections simultaneously on the same clock cycle. Addressing means within each section then routes the word to the appropriate memory circuit within the section. In a read operation each section loads its register simultaneously, after which the data words are transmitted in a serial fashion from register to register out of the memory to the port. The memory circuits within each section are organized into a plurality of banks, each of which may be addressed independently of one another, so that a section may capture at least one word per clock cycle. A further circuit is provided to reverse the order of words received from the port during a write operation to cause the words to be in proper order when read from the memory.

Solid state storage device

Growing community of inventors

Chippewa Falls, WI, United States of America

James W Sundet