International Business Machines Corporation

James W Plant

Stefan P Jackowski

James T Moyer

David N Gooding

Thomas J Dvorak

David J Lowdermilk

A failure detection apparatus detects the existence of an abnormal circuit condition in a circuit which causes a subsequently transmitted data byte to be transmitted from one integrated circuit to another integrated circuit out of sequence relative to a previously transmitted data byte. Even and odd data bytes are received by the first integrated circuit with odd parity. However, the even data byte is transmitted from the first integrated circuit to the second integrated circuit, along existing interface lines extending between the integrated circuits, with odd parity. The parity bit of the odd data byte is inverted, the odd data byte being transmitted along the existing interface lines with even parity. An exclusive OR gate in the second integrated circuit receives the parity bit of the even data byte and passes the parity bit without inversion in response to a first state of a clock signal from an odd latch; however, the exclusive OR gate, upon receipt of the odd data byte, re-inverts the parity bit of the odd data byte in response to a second state of the clock signal. A parity checker compares the data bits of the incoming even and odd data bytes with the parity bit generated by the exclusive OR gate and generates an error check signal representative of the receipt of the subsequently transmitted data byte transmitted out of sequence relative to the previously transmitted data byte when the combined parity of the data bits and parity bit at the input of the parity checker is not odd.

Failure detection method and apparatus

A microcontrol extension mechanism for increasing the number of control actions for a processor data flow section in the same manner as could be accomplished by increasing the length of the microwords in the processor control store but without actually increasing the length of such microwords. The additional control actions are obtained by means of a relatively small read only storage array having stored therein a separate pluralbit mode word for each of the different machine macroinstruction operation codes. This read only storage array is directly addressed by the operation code of the macroinstruction being processed to cause a read out of its corresponding mode word, which mode word is then set into a mode register. The output lines of the mode register are coupled to the desired additional control points in the processor data flow section. A second small read only storage array is also provided for storing the starting addresses for the different operation code microroutines in the processor control store. During the fetching of the macroinstruction to be processed, the operation code portion of such macroinstruction is used to address this second read only storage array to cause it to supply to the address register for the control store the starting address for the sequence of microwords to be used in executing such macroinstruction.

Growing community of inventors

Endwell, NY, United States of America

James W Plant