Freescale Semiconductor,inc.

Motorola Corporation

Other

AT&T Intellectual Property I, LP

Nxp Usa, Inc.

At&t Knowledge Ventures, LP

James W Miller

Michael A Stockinger

Michael G Khazhinsky

Kevin John Hess

Susan H Downey

Melanie Etherton

Larry B Pearson

Jeffrey L Brandt

Stephen Mark Mueller

Geoffrey B Hall

Robert Scott Ruth

Alex P Gerdemann

Chu-Chung Lee

James M Doherty

Mohamed S Moosa

Robert Randal Bushey

Benjamin Anthony Knott

John M Martin

Kurt M Joseph

Theodore B Pasquale

Tu-Anh N Tran

Scott H Mills

Fujio Takeda

Cheng Choi Yong

Jonathan M Phillippe

Scott Wallace Miller

Leo Mathew

Douglas F Reynolds

Aaron Bangor

Burton Jesse Carpenter

Jeremy Charles Smith

Troy L Cooper

Bradley Paul Smith

Anthony G Dunne

Aykut Dengi

Percy V Gilbert

Stephen G Jamison

Paul G Tsui

Joseph Y Chan

Matthew D Akers

Nhat Dinh Vo

Jose A Camarena

Cynthia Ann Torres

Alexander Alekseevich Krasin

James Patrick Johnston

Harold A Downey

Kuo-Hsuan Meng

Dae Y Hong

Kendall Dewayne Phillips

Martin J Bayer

Daniel J O'Hare

Paul J Sheridan

Jeannie Han Millaway

Bryan D Preble

James C Weldon

Vishnu G Kamat

Alexey Gilgur

An ESD protection circuit includes a detection circuit for detecting an ESD event. The detection circuit includes two current mirrors each for providing two detection signals. The ESD protection circuit includes driver circuitry that produces trigger signals to clamp circuits that make conductive the clamp circuits in response to an ESD event based on the detection signals from the current mirrors.

ESD protection circuit providing multiple detection signals

An integrated circuit including ESD circuitry that is shared among more than one terminal segment of the integrated circuit to discharge current from an ESD event on any of the terminal segments. The shared ESD circuitry includes a clamp circuit that is coupled to power buses of each segment to discharge current from ESD events on each segment. The shared ESD circuitry includes a trigger circuit that is coupled to nodes coupled to terminals of each segment to detect an ESD event on each segment.

Shared ESD circuitry

An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.

Electrostatic discharge protection system

Boosted Electrostatic Discharge (ESD) clamp circuit with high effective holding voltage. In some embodiments, an integrated circuit may include a trigger circuit operably coupled to a first voltage bus and to a reference bus; a diode including an anode terminal operably coupled to a second voltage bus, the second voltage bus distinct from the first voltage bus; a transistor including a gate operably coupled to an output terminal of the trigger circuit, a drain operably coupled to a cathode terminal of the diode, and a source operably coupled to the reference bus; and an input/output (I/O) cell operably coupled to the first voltage bus, the second voltage bus, and the reference bus.

Electrostatic discharge (ESD) clamp circuit with high effective holding voltage

An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network.

I/O cell ESD system

Customer communications can be controlled in accordance with customized rules. An initial menu includes options to modify an existing rule or create a new rule for controlling customer communications. An initial selection criteria menu includes options to indicate whether the new customized rule will be built using a preexisting template or starting from initial blank rule criteria. A list of preexisting templates for creating new customized rules can be provided, and input to populate a selected template can be accepted. Initial blank rule criteria for creating new customized rules can also be provided, including initial criteria and rule conditions for selected initial criteria. Communications are processed in accordance with the stored new customized rule.

Incoming and outgoing call control customization

A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.

Patterning a gate stack of a non-volatile memory (NVM) with formation of a metal-oxide-semiconductor field effect transistor (MOSFET)

Customer communications can be controlled in accordance with customized rules. An entry menu includes options to modify an existing rule or create a new rule for controlling customer communications. An initial selection criteria menu includes options to indicate whether the new customized rule will be built using a preexisting template or starting from initial blank rule criteria. A list of preexisting templates for creating new customized rules can be provided, and input to populate a selected template can be accepted. Initial blank rule criteria for creating new customized rules can also be provided, including initial criteria and rule conditions for selected initial criteria. Communications are processed in accordance with the stored new customized rule.

Embodiments of the present disclosure provide an integrated circuit (IC) or semiconductor device. This semiconductor device includes a number of I/O pads or bumps on an outer surface of the semiconductor device, a number of electrostatic discharge (ESD) protection cells and functional modules. Individual ESD protection cells couple to and are downstream of individual I/O pads. Functional modules coupled to and are downstream of individual ESD protection cells. The ESD protection cells protect circuitry within the functional module from electrostatic discharge events. A rail clamp may provide an ESD discharge path between a first power supply bus and a second power supply bus. The ESD protection cells may be collected in groups to form clusters (with linear or irregular placement patterns). These clusters may be distributed autarchically across the semiconductor device overlapping one or more functional modules or within spaces or gaps between the functional modules.

Distribution of electrostatic discharge (ESD) circuitry within an integrated circuit

A method is provided for customizing a call control rule by a subscriber at a graphical user interface. The method includes providing a first display, including multiple conditions relating to identifying calls involving the at least one telephone number, and receiving a first selection of at least one identifying condition. The method further includes providing a second display, including multiple call dispositions relating to processing the calls based on the at least one selected condition, and receiving a second selection of at least one call disposition. The identifying condition and the call disposition are stored as the call control rule in association with the telephone number, and calls involving the telephone number are processed in accordance with the stored call control rule. The method may also include providing a third display describing the call control rule contemporaneously with receiving the first and second selections.

An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance.

High frequency interconnect pad structure

A system and method for providing customer activities while in queue allows for one or more customers to interact with one or more customer activities while waiting to speak with a live agent. The customers engage the customer activities while holding in a queue where the customer activities reduce the boredom, frustration, and perceived hold duration associated with holding to speak to a live agent. The customers are offered one or more options of the customer activities to interact with and the system and method monitors the customers' selections and interaction with the customer activities. As agents become available, each customer is transferred to an agent along with information regarding the customer's interaction with a selected customer activity. Upon completion of the interaction between the agent and the customer, the customer has the option to return to the selected customer activity and continue interacting with the selected customer activity.

System and method for providing customer activities while in queue

A packaging assembly (), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die () by using an encapsulated patterned leadframe conductor () that is disposed over the die () and bonded to a plurality of bonding pads () formed in a BGA carrier substrate () and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.

Power lead-on-chip ball grid array package

A system and method of publishing contact information is disclosed. In a particular embodiment, the method includes receiving a command to publish a collection of contacts to a plurality of recipients, where the collection of contacts is associated with a network address book of a sender. The method also includes receiving a distribution list that identifies the plurality of recipients. Additionally, the method includes sending a notification to each of the plurality of recipients, where the notification includes an invitation to subscribe to the collection of contacts. The method also includes sending the collection of contacts to at least one of the plurality of recipients who subscribes to the collection of contacts.

System and method of publishing contact information

A semiconductor device () is provided which comprises a substrate (); a semiconductor device () disposed on said substrate and having a first major surface; a first metal strap () which is in electrical contact with said substrate and which is adapted to provide power to a first region () of said semiconductor device; and a second metal strap () which is in electrical contact with said substrate and which is adapted to provide ground to a second region () of said semiconductor device.

Interconnect for chip level power distribution

Growing community of inventors

Austin, TX, United States of America

James W Miller