Cornell Research Foundation Inc.

International Business Machines Corporation

Arizona Board of Regents, a Body Corporate

University of California

James W Mayer

Evan G Colgan

Jian Li

Jeffrey P Gambino

Michael A Nastasi

Terry L Alford

Noel C MacDonald

Vincent B Pizziconi

Leslie H Allen

Timothy E Levine

David Stanasolovich

James P Spallas

Martin Mitan

David P Pivin, Jr

Hyunchul Kim

Douglas C Thompson, Jr

Daniel Adams

John H Das

An electronic apparatus uses a single crystalline silicon substrate disposed adjacent to a flexible substrate. The electronic apparatus may be a flexible flat panel display, or a flexible printed circuit board. The flexible substrate can be made from polymer, plastic, paper, flexible glass, and stainless steel. The flexible substrate is bonded to the single crystalline substrate using an ion implantation process. The ion implantation process involves the use of a noble gas such as hydrogen, helium, xenon, and krypton. A plurality of semiconductor devices are formed on the single crystalline silicon substrate. The semiconductor devices may be thin film transistors for the flat panel display, or active and passive components for the electronic device.

Flexible electronics using ion implantation to adhere polymer substrate to single crystal silicon substrate

Direct focused ion beam (FIB) mixing is given as a method for patterning of metal silicide structures on a silicon surface. This technique allows the fabrication of submicron structures without the use of resist-based lithography methods. VLSI containing metal silicide connects, interconnects and structures may be prepared by the method. Fast semiconductor devices having good circuit speed and reduced RC time delay including the technologies MEMS, MOSFET, CMOS, pMOS, nMOS and BiCMOS result.

Direct patterning of nanometer-scale silicide structures on silicon by ion-beam implantation through a thin barrier layer

Processing of hydroxylapatite sol-gel films on titanium alloy bone prostheses. A method utilizing non-line-of-sight ion beam implantation and/or rapid thermal processing to provide improved bonding of layers of hydroxylapatite to titanium alloy substrates while encouraging bone ingrowth into the hydroxylapatite layers located away from the substrate, is described for the fabrication of prostheses. The first layer of hydroxylapatite is mixed into the substrate by the ions or rapidly thermally annealed, while subsequent layers are heat treated or densified using ion implantation to form layers of decreasing density and larger crystallization, with the outermost layers being suitable for bone ingrowth.

Processing of hydroxylapatite coatings on titanium alloy bone prostheses

A micrometer scale emitter tip or array is disclosed having precisely located tips and surrounding gates. A silicide on the tips reduces tip work function.

Silicon tip field emission cathodes

The present invention features a process and a resulting article in which copper-based multilevel interconnects are fabricated. The copper-based multilevel interconnect formed by the inventive process first includes the process step of depositing a pattern of copper lines upon or in an applicable substrate, such as silicon dioxide. The copper lines are approximately one micron thick. The lines are coated with approximately 50 to 100 nm of titanium by sputter deposition, and undergo subsequent annealing at approximately 300.degree. C. to 400.degree. C. in an argon ambient. The titanium and copper layers are annealed to provide a Cu.sub.3 Ti alloy at the copper/titanium junction. The unreacted titanium between the copper features is then stripped away by dry etching with fluorine-based etch. The remaining Cu.sub.3 Ti alloy is subsequently transformed into TiN(O) and copper by a rapid thermal annealing in an NH.sub.3 atmosphere at an approximate temperature of below 650.degree. C., and then usually at temperatures ranging from between 550.degree. C. to 650.degree. C. for approximately five minutes. The copper lines are thereby capped with a layer of TiN(O), since oxygen is incorporated into the TiN layer during the heat treatment. The TiN(O) layer is more effective as a diffusion barrier than is TiN.

Self-aligned process for capping copper lines

The present invention features low-temperature, self-encapsulated, copper interconnect lines on silicon substrates of Ultra-Large Scale Integration (ULSI) circuits. The interconnect lines are a product of a process that includes the following steps: (a) alloying the copper with titanium in an approximate 10 atomic weight percentage of titanium; (b) depositing a layer of the copper/titanium alloy upon a silicon dioxide/silicon substrate of a ULSI circuit; (c) patterning the copper/titanium layer to form interconnect lines on the substrate; (d) forming a titanium rich surface film on the copper interconnect lines by rapid heating of the copper/titanium interconnect lines at an approximate ramping rate of between 60.degree. and 80.degree. C./minute; and (e) nitriding the titanium rich surface of the interconnect lines in an ammonia atmosphere at low temperatures in an approximate range of between 450.degree. to 650.degree. C. for about 15 to 40 minutes, to form a titanium nitride encapsulating layer about said copper interconnect lines.

Process for fabricating copper interconnects in ultra large scale

An improved process for preparing selective deposition of conductive metals on disilicide encroachment barriers allows the construction of integrated circuit components wherein the metal/disilicide interface is substantially free of O and/or F contamination. The level of interfacial oxygen and/or fluorine contamination in the selective W deposition on the TiSi.sub.2 was substantially reduced or eliminated by first forming a C49 TiSi.sub.2 phase on a substrate, selectively depositing W on the C49 TiSi.sub.2 phase and thereafter annealing at a (minimum) temperature sufficient to convert the high resistivity phase C49 TiSi.sub.2 to the low resistivity phase C54 TiSi.sub.2.

Selective deposition of tungsten on TiSi.sub.2

Growing community of inventors

Phoenix, AZ, United States of America

James W Mayer