Bull Hn Information Systems, Inc.

Honeywell Information Systems Inc.

Honeywell Bull, Inc.

Lsi Corporation

Bull Hn Inforamtion Systems Inc.

James W Keeley

George J Barlow

Richard A Lemay

Chester M Nibby, Jr

Thomas F Joyce

Richard C Zelley

Virendra S Negi

Robert V Ledoux

Elmer W Carroll

Arthur Peters

Thomas S Hirsch

Douglas E Sanders

Andrew Hyonil Chong

Keith L Petry

Jian-Kuo Shen

Richard P Kelly

Robert C Miller

Kenneth E Bruce

John L Curley

Bruno DiPlacido, Jr

Edwin P Fisher

Victor M Morganti

Wallace A Martland

Robert V Ledoux, Deceased

Martin M Massucci

Daniel W Meyer

Ju-Ching Tang

Apparatus and methods improved fair access to a Fiber Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC-AL communication medium. Thus all devices on the loop whether coupled directly or through a bridge device can be assured fair access to the loop when there are simultaneous requests during an open access window.

Apparatus and methods for access fairness for a multiple target bridge/router in a fibre channel arbitrated loop system

Apparatus and methods for an enhanced bridge device for coupling multiple non-Fiber Channel storage devices to a Fiber Channel Arbitrated Loop (FC-AL) communication medium. Features and aspects hereof provide for FC-AL enhanced circuits for processing loop port bypass (LPB) and loop port enable (LPE) primitive sequences addressed to any target arbitrated loop physical address (T-ALPA) associated with a storage device coupled with the bridge regardless of the present bypassed/non-bypassed status of other T-ALPAs processed by the bridge device and associated with other storage devices coupled with the bridge device.

Bridge apparatus and methods for coupling multiple non-fibre channel devices to a fibre channel arbitrated loop

A multiprocessor computer system includes a number of processors, each processor having an interrupt mechanism and connecting in common to a system bus over which interrupt requests are communicated. When a processor accepts an interrupt request from another processor, it generates an acknowledge response on the system bus. If such processor contains a previous and pending interrupt request of an equal or higher priority level, it generates a not acknowledge response on the system bus and refuses the interrupt request. At the completion of servicing an interrupt request, each processor places on the system bus, an interrupt completed command including an address identifying such processor, a code designating a priority level to which it has switched and a code indicating that the processor has completing servicing an interrupt request. Each interrupt mechanism further includes interrupt retry means containing a refused interrupt register means for storing the channel address of the processor generating the not acknowledge in response and the priority level code contained in the interrupt request, and a level monitor logic unit connected to the system bus. The level monitor logic unit detects interrupt completed commands and compares the channel address and priority level code in the interrupt completed command to channel address and level code stored in the refused interrupt register means. When the processor channel addresses match and the level code is less than the level stored in the refused interrupt register means, the monitor logic unit generates a retry interrupt output. The processor retries the corresponding previously refused interrupt request upon receipt of the retry interrupt output.

Apparatus and method for providing more effective reiterations of

A processing unit couples to a system bus and includes a microprocessor which tightly couples to a local memory. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which couples to the microprocessor and to the system bus. The EEPROM unit stores in first and second separate regions, on-board diagnostic (OBD) routines and boot routines, respectively. The OBD routines are organized into a plurality of categories or phases. The processing unit includes a register accessible only by the microprocessor which, under the control of the OBD routines, is loaded with a number of predetermined values at the beginning of each individual OBD routine for identifying a particular phase and subphase of testing to be performed. Means coupled to the register is directly connected to display a first phase portion of the contents of the register for indicating during which phase of testing a failure occurred. The phase and subphase contents of the register are used to identify the actual test which failed. This information provides an index into a test dictionary which indicates the specific component or group of components which failed.

On-board diagnostic testing

A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.

Power-on sequencing apparatus for initializing and testing a system

A method and apparatus provides fast synchronization of asynchronous signals to use by a synchronously operated device by quantizing the delay of an input clocked bistable device which receives and stores the asynchronous signal in response to a first synchronous clock pulse so that such input clocked bistable device has a metastable time period which is less than a predetermined maximum delay period. The output signal of the input clocked bistable device is connected directly to as an input to an asynchronously operated logic circuit part selected to provide a resulting output signal corresponding to the result of performing a logical operation on the output signal within a predetermined minimum time period. The resulting output signal is directly applied to the input of another synchronously operated bistable device which stores the resulting output signal in response to the next occurring synchronous clock pulse corresponding to a time period which is greater than the time of the metastable time period, minimum delay of the logic part and preset of time of such bistable device.

Fast synchronization of asynchronous signals with a synchronous system

A processor couples to a system bus and includes a high performance microprocessor which tightly couples to a local memory. The processor is organized at the interface level into a plurality of interface sections which include a corresponding number of state machines for enabling the simultaneous processing of a plurality of different types of transactions or requests under all conditions. One interface section is organized to include the system visible registers which are accessible for reading and writing by I/O commands received from the system bus. Another section processes memory commands received from the system bus while a further section processes read/write and I/O commands issued to the system bus by the processor.

Bus interface state machines with independent access to memory,

A bus interface priority network provides access to a system bus by a plurality of different types of requestors as a function of the types of transactions they are required to process. The network includes programmable circuit for identifying the type of requestor and selecting a delay for accessing the system bus on the basis of requestor type thereby eliminating the need to adjust timing to the slowest requestor.

Programmable system bus priority network

A multiprocessor computer system having a first processor having a first interrupt mechanism for generating interrupt requests, a second processor having a second interrupt mechanism, and a system bus for communicating interrupt requests from the first processor to the second processor. The second interrupt mechanism is responsive to an interrupt request by generating an acknowledge response on the system bus when the second processor accepts the interrupt request and generating a not acknowledge response on the system bus when the second processor contains a previous and pending interrupt request of higher level and refuses the interrupt request. The second interrupt mechanism is responsive to the completion of servicing of an interrupt request by the second processor by placing on the system bus an interrupt completed command, which includes an address identifying the second processor and a code indicating that the second processor has completing servicing an interrupt request. The first processor includes an interrupt retry means, which includes a refused interrupt register means responsive to a not acknowledge response from the second processor in response to an interrupt requested from the first processor for storing the channel number of the second processor, and level monitor logic connected from the system bus.

A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.

Data processing system having a bus command generated by one subsystem

A multiprocessor computer system includes first processors, second processors, a system management means for performing system management functions, including detecting pending power shut-downs and sending power shut-down messages addressed to each of the first processors warning of pending power shut-downs, and a system bus for communication between the first and second processors and the system management means, including the communication of pending power shut-down messages. The first processors include interrupt handling means responsive to pending power shut-down messages for executing power shut-down routines for placing the first processors into a known state before power termination, but the second processors inherently do not include a power shut-down capability. In each of the second processors, a power shut-down means is provided to place the second processors in a known state before a power termination, including a bus monitor connected from the system bus and responsive to any power shut-down message addressed to a first processor for generating an output indicating the occurrence of a power shut-down message to a first processor. The second processor also includes non-maskable interrupt logic connected from the power shut-down message output of the bus monitor and responsive to the power shut-down message output of the bus monitor for generating a non-maskable interrupt output to the second processor. The second processor is in turn responsive to a non-maskable interrupt output of the non-maskable logic for querying the non-maskable logic to determine the nature of the interrupt, and responsive to the indicated occurrence of a power shut-down message to any first processor for executing a power shut-down routine for placing the second processor in a known state before the termination of power.

Means for providing a graceful power shut-down capability in a

A processing unit tightly couples to a system bus which utilizes a split cycle bus protocol and includes a local memory which is accessible from such bus. The local memory couples to a high speed synchronous bus which operates according to a predetermined bus protocol. The processing unit includes a state machine which couples to the high speed synchronous bus and to the asynchronous system bus. The state machine emulates the predetermined bus synchronous protocol in transferring commands issued to the local memory from the system bus which uses the split cycle protocol.

Bus controller having state machine for translating commands and

A processing unit tightly couples to a system bus and includes a local memory which is accessible from such bus. The processing unit includes a high performance microprocessor which tightly couples to the local memory through a high speed synchronous bus shared with a plurality of synchronous state machines. A microprocessor internal bus state machine and the plurality of state machines control local bus accesses for transferring commands generated by the microprocessor and commands transferred from the system bus under the control of an external state machine for execution by a local memory state machine and the processor state machine, respectively, which also couples to the system bus.

Processing unit having multiple synchronous bus for sharing access and

A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.

Processor bus access

A high performance microprocessor has associated therewith, protocol monitoring apparatus for monitoring all of the commands issued by the microprocessor and detecting when the protocol was not completed properly or completed within certain preestablished periods of time. When the monitor/timing circuits detect a protocol error, the monitoring apparatus operates to generate an output control signal which unwedges the microprocessor enabling it to continue further processing. Additionally, the monitoring apparatus includes a register for storing the address and command that the microprocessor was executing at the time of the protocol error. The same register is also used to capture address and command information for any other type of error.

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Nashua, NH, United States of America

James W Keeley