Tactical Fabs, Inc.

Lsi Logic Corporation

International Business Machines Corporation

James W Hively

Mammen Thomas

Richard L Bechtel

Gobi R Padmanabhan

Visvamohan Yegnashankaran

John P Daane

Michael DiPietro

Joseph M Zelayeta

A semiconductor package having positioned therein a protection layer which protects the integrated circuit chip from electrostatic discharge (ESD) damage. The protection layer is made of a material that has at steady state a high electrical resistance, but when a high ESD potential is applied to it, it becomes highly conductive. A preferred material is SurgX.TM., which is a polymer. The layer is positioned to shunt the potential away from the chip, and can be positioned operatively between a signal lead and a power plane or between different signal leads. That is, the protection layer can be sandwiched between the lead and the conductive member, or the lead can be within the layer. Another preferred construction incorporates the protection material in a tape construction as a thin layer sandwiched between and bonded to a layer of leads and a ground plane.

Method of fabricating a microelectronic package having polymer ESD

Microelectronic package with polymer ESD protection

Microelectronic devices are formed on a substrate of an integrated circuit. An electrically conductive ground or power plane, and an ElectroStatic Discharge (ESD) protection layer are formed on the substrate. Terminals such as solder ball or wire bond pads are formed on the substrate, and are electrically connected to the devices. The protection layer is patterned such that portions thereof are disposed between the terminals and the plane to define vertical electrical discharge paths. The protection layer is formed of a material such as SurgX.TM. which is normally dielectric, and is rendered conductive in the discharge paths by an electrostatic potential applied to the terminals during an ESD event to shunt the electrostatic potential from the terminals to the plane. Alternatively, the protection layer can be formed between the terminals to define lateral discharge paths.

Microelectronic device with thin film electrostatic discharge protection

A socket for testing an integrated circuit ball grid array package having external contacts formed by an array of solder balls is formed with a flexible bladder in the socket bottom. The upper side of the bladder has a test contact pattern that matches the pattern of the solder balls on the package. The side of the bladder carrying the test contact pattern is formed of conventional flexible circuit tape having contacts of spherical, conical or cylindrical shape formed thereon by conventional techniques, with circuit traces also formed on the flexible circuit tape extending to the outside of the socket for connection to test circuitry. Inflation of the bladder drives its test contact pattern against the solder balls of a package held in the socket and forces the flexible test contact substrate of the bladder to conform to any non-planar configuration of the ball grid array.

Test socket for testing integrated circuit packages

A code mechanism is provided in an integrated circuit for identifying the integrated circuit such as by serial number or for use in enabling the circuit and equipment housing the circuit. Fuses, antifuses, and programmable field effect transistors are used in an array for establishing a code. The code can be established by loading a register through the array and then reading the register. Alternatively,the contents of the register can be compared with a code provided by a user to enable the circuit. In another embodiment, a ROM is loaded with a table of encryption keys, and a user addresses the ROM by loading an address in a register or in a RAM.

Semiconductor chip having identification/encryption code

This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements. As another novel feature, the structure may include two or more address ports, which may simultaneously address different banks of the repeating elements. The plural address port feature is particularly useful for automatic refreshing of dynamic random access memories (DRAMs) and/or for plural addressing with other memory types. The architecture provides for flexibility in the final functional organization of wafer scale devices, which is determined at the time the via level is customized. An overall reduction of overhead control circuitry and the reduced size of the repeated block provides for higher total density per wafer than is achievable with conventional single chip integrated circuits using the same level of manufacturing technology. More than one discretionary via layer and more than one bus layer may be provided.

Very high density wafer scale device architecture

This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure. The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing for good and bad elements. The structure may include two or more address ports, which may simultaneously address different banks of the repeating elements, which feature is particularly useful for automatic refreshing of dynamic random access memories (DRAMs) and/or for plural addressing with other memory types. The architecture provides for flexibility in the final functional organization of wafer scale devices, which is determined at the time the via level is customized. An overall reduction of overhead control circuitry and the reduced size of the repeated block provides for higher total density per wafer than is achievable with conventional single chip integrated circuits using the same level of manufacturing technology.

This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements.

A package for housing a large scale semiconductor integrated circuit structure, such as a wafer or an assemblage of chips in a hybrid configuration, comprises a heat spreading and dissipating base plate to which the wafer or hybrid circuit is directly bonded. Electrical connections from the periphery of the package interior to the wafer are preferably made with equal length TAB (Tape Automated Bonding) strips connected to electrically conductive pads located along a diameter of the wafer or the centerline of the hybrid circuit. If hermeticity is desired, the integrated circuit structure is encircled by a boundary strip of sandwich construction through which signals are routed, and to which a lid is attached. For hermeticity, the integrated circuit structure is surrounded on all sides with a barrier combining metal and ceramic; the remainder of the package may be constructed from conventional printed circuit board materials. The package can be made arbitrarily large without encountering the problems typically associated with hermetic structures which utilize large areas of ceramic materials.

Package for an integrated circuit structure

A package for multiple semiconductor integrated circuit chips uses an interconnect structure manufactured by semiconductor processing techniques to provide dense interconnections between chips and to input/output terminals. Chips are thermally connected to a Kovar or molybdenum heatsink. The interconnect structure is constructed by fabricating multiple layers of interconnect metallization on an optically flat glass (or other dielectric) surface patterned into lines and separated by smoothed glass dielectric. The metallization lines are interconnected by vias and lead to pads which are connected to chip pads and to exterior pins or wiring. An interconnect frame allows access to the chips and the interconnect structure to effect wire bonding of the chips to the metallization and provide sealable cavities for the chips. Elastomeric connectors extend through and are aligned by the frame to connect pads on the interconnect structure top to traces on a mother board to which the package is mounted. Chip bonding plates allow chips to be removed from the package and replaced when found defective.

Growing community of inventors

Sunnyvale, CA, United States of America

James W Hively