Level One Communications, Inc.

Clare Micronix Integrated Systems, Inc.

James W Everitt

Hiroshi Takatori

James G Parker

Daniel L Ray

Robert Edward DeCaro

Patrick N Dennehey

Kenneth G Buttle

Paul James Hurst

David S Nack

A system for providing balanced currents at locations in devices requiring accurate, matched and repeatable current sources, for example visual displays having arrays of light-emitting sources. In one embodiment, the system provides closely balanced currents flowing through column drivers located at or near end regions of a display area. The system allows for more closely matching currents at adjacent columns in a device such as a visual display, wherein the currents are driven by separate driver circuits, thereby eliminating discontinuity in brightness across the entire display area and providing higher quality visual display devices. Another embodiment provides closely balanced currents flowing through column drivers located at or near end regions of a display area. The system additionally allows for balancing currents at adjacent columns or regions throughout the device.

System for current matching in integrated circuits

A method of providing balanced currents at locations in devices requiring accurate, matched and repeatable current sources, for example visual displays having arrays of light-emitting sources. In one embodiment, the method provides closely balanced currents flowing through column drivers located at or near end regions of a display area. The method allows for more closely matching currents at adjacent columns in a device such as a visual display, wherein the currents are driven by separate driver circuits, thereby eliminating discontinuity in brightness across the entire display area and providing higher quality visual display devices. Another embodiment provides closely balanced currents flowing through column drivers located at or near end regions of a display area. The method additionally allows for balancing currents at adjacent columns or regions throughout the device.

Method of current matching in integrated circuits

A pulse width modulation driver for an organic light emitting diode display. One embodiment of a video display comprises a voltage driver for providing a selected voltage to drive an organic light emitting diode in a video display. The voltage driver may receive voltage information from a correction table that accounts for aging, column resistance, row resistance, and other diode characteristics.

Method of providing pulse amplitude modulation for OLED display drivers

System for providing pulse amplitude modulation for OLED display drivers

A method and apparatus to calibrate an LED matrix display such that a driver will provide a proper precharge voltage to LED elements within the display during a scan period. A current is driven through a calibration element, and a voltage reflecting the steady-state element voltage is measured and stored as a calibration value. A processor controls whether to precharge during the calibration cycle, and determines when the calibration cycle is completed. During subsequent normal scans, a driver applies a voltage based on the stored calibration value to rapidly precharge parasitic capacitance associated with a display element to a proper value, and also drives a selected current through the device.

Matrix element voltage sensing for precharge

A phase-locked loop circuit for providing a tightly controlled capture range for locking an output signal to a data signal, while also providing a wide frequency capture range for initially pulling the output signal within this narrow, predetermined frequency range. The apparatus detects a frequency difference between at least one reference signal and an output signal, and generates a frequency error signal in response to the frequency difference. A phase difference is detected between a received input signal and the output signal, and a phase error signal is generated in response to the phase difference. The frequency error signal and the phase error signal are combined to control the frequency of the output signal by controlling an input-controlled oscillator.

Emulating narrow band phase-locked loop behavior on a wide band phase-locked loop

A phase-locked loop circuit is disclosed which exhibits a wide capture range and a low quality factor (Q) to prevent ringing and improve stability without adding area, increasing power consumption or increasing noise levels. The phase-locked loop includes a comparator to generate an error signal, an oscillator which generates an output signal in response to a control signal and a loop filter which generates the control signal based on the error signal. The loop filter includes a first integrator operatively coupled through a threshold limit detector to a second integrator. The threshold limit detector supplies an electric charge to the second integrator only when the first integrator is proximate to either an upper limit or a lower limit of the first integrator's operating range. The oscillator generates the output signal which tracks the input reference signal frequency as an integer multiple of the input reference signal frequency. The oscillator generates the output signal in response to varying current levels of the control signal. The loop filter further includes a pump-up and a pump-down charge pump that act in tandem under activation by the threshold limit detector. The loop filter includes a duty cycle limiter switch that limits the supply of the charge to the second integrator to a predetermined time period.

Modified third order phase-locked loop

A baud rate sampling receiver, for reducing signal overshoot and improving equalization of a communications channel. The receiver filters an input signal, samples the filter output signal at the baud rate, continuously monitors the filter output signal for overshoot using a latching comparator circuit, and controls filter parameters based upon the sampling and monitoring using a filter control. The latching comparator circuit includes a positive latching threshold comparator circuit and a negative latching threshold comparator circuit. Each of these comparator circuits provides a threshold control bit to the filter control in response to a detection of signal overshoot. While the filter control also receives information about the filtered output signal from a sampling circuit, the threshold control bits indicate to the adaptive filter control immediately, rather than at the next sample point, when signal overshoot is present. The filter control responds by appropriately adjusting filter parameters such as high frequency boost.

Method and apparatus for modified baud rate sampling

The analog adaptive equalizer provides convergence of an error signal by decoupling the error canceller, the automatic gain control and the filter to provide truly adaptive error minimization. The invention includes an automatic gain control (AGC) circuit for providing broadband amplification of an input signal to generate an AGC output signal, a filter for receiving the AGC output signal and providing high frequency signal conditioning to generate a filter output signal, an error detection circuit for generating an error signal representing the difference between the filter output signal and an expected output signal and a calculator for receiving the error signal and providing a gain correction signal to the automatic gain circuit to adjust the gain of the automatic gain circuit and a filter control signal to adjust the filter range of the filter, the gain correction signal and the filter control signal being used to cancel the error signal. The calculator further comprises a first in, first out buffer for providing a history of the expected output signal to the calculator.

Analog adaptive equalizer with gain and filter correction

A timing recovery apparatus for recovering the timing from sparse timing information in multi-level or partial response codes. The timing recovery apparatus includes a switch for sampling an incoming line code signal according to a selectable sample rate, a feed forward equalizer for filtering the sampled signal, a decision feedback equalizer for cancelling intersymbol interference in the filtered signal and for recovering the timing in the sampled signal. The timing recovery circuit creates a phase correction signal in response to a signal received from the feed forward equalizer and thereby control the sample rate of the sample switch so that the signal-to-noise ratio at the node before the decision is maximized. The voltage controlled crystal oscillator may be controlled within a certain frequency range by using a second phase detector which compares the phase of the signal controlling the sampling of the incoming line code with a reference clock.

Phase-locked loop timing recovery circuit

A digital-to-analog (D/A) converter eliminates matching requirements and does not generate harmonics or noise. The D/A converter has an array of injectors for converting an input word to an analog voltage. A plurality of clocked switches discharge the injector array and the feedback path when switched into a first phase position and transfer the injector signal across the feedback path to the output of the D/A converter when switched to a second phase position. The conversion period, the time in which the digital input word is converted to an analog output voltage, is divided into N-1 subperiods. Each injector is enabled once or not at all for each subperiod such that the weighted signal injected during a single conversion period is constant and such that all the injectors in the array contribute an equal amount of signal during a conversion period.

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Granite Bay, CA, United States of America

James W Everitt