Intel Corporation

Other

James W Alexander

Devadatta V Bodas

Rajat Agarwal

Kai Cheng

Muralidhar Rajappa

Andy Hoffman

Howard S David

Justin J Song

Son H Lam

Krishna Kant

Kuljit Singh Bains

Pete D Vogt

Ian M Steiner

Thomas J Holman

Malay Trivedi

Mohan Nair

Stanley Steve Kulick

Suresh S Chittor

Dennis W Brzezinski

Bruce A Christenson

Mark A Heap

Neven M Abou Gazala

Ren Wang

Christian Maciocco

Rahul Khanna

Prashant R Chandra

Eugene Gorbatov

Richard Paul Mangold

Ulf Hanebutte

Joseph Murray

James Steven Burns

Muthukumar Swaminathan

Joseph A Schaefer

Edward R Stanford

Suneeta Sah

Ahmad A Samih

Elliot D Garbus

Tsung-Yuan Charlie Tai

Henk G Neefs

Robert Richard Bock

Buck Gremel

Michael J Tripp

Ramkumar Nagappan

Pinkesh J Shah

Louis J Johnson

Sunil K Mahawar

Stephen J Peters

Gopikrishna Jandhyala

Ronald J Whitsel

Joaquin B Romera

Terri A Danowski

Douglas D Yoder

Lionel S Smith, Jr

Vijayendra K Hoskoti

Joaquin Romera

A non-transitory computer readable storage medium having stored thereon instructions, the instructions being executable by one or more processors to perform operations including: receiving, by a calibration module executed by the one or more processors, a calibration request including (i) a workload type, (ii) a list of compute nodes belonging to a distributed computer system, and (iii) one or more frequencies; responsive to identifying the workload type as a clustered workload type, instructing a plurality of compute nodes on the list of compute nodes to begin processing a workload of the workload type; and responsive to identifying the workload type as a clustered workload type, instructing a compute node on the list of compute nodes to begin processing the workload of the workload type is shown.

Method and apparatus to generate and use power, thermal and performance characteristics of nodes to improve energy efficiency and reducing wait time for jobs in the queue

A non-transitory computer readable storage medium storing instructions executable by one or more processors of a distributed computer system to perform operations including determining whether a power consumed by the distributed computer system is greater than a power allocated to the distributed computer system, responsive to determining the power consumed by the distributed computer system is greater than the power allocated to the distributed computer system, determining whether all jobs being processed by the distributed computer system are processing at a lowest power state for each job, wherein a job includes one or more calculations performed by the one or more processors of the distributed computer system and responsive to determining all jobs being processed by the distributed computer system are processing at a lowest power state for each job, suspending a job having a lowest priority among all jobs being processed by the distributed computer system is shown.

Methods and apparatus to manage jobs that can and cannot be suspended when there is a change in power allocation to a distributed computer system

A method is described. The method includes receiving an indication of an activity of load circuitry of a power supply. The method includes, in response to the indication, generating a first signal that describes the activity and a second signal that describes whether the event is initiating or completing. The method includes determining a weight amount from the first signal and adjusting a credit count by the weight amount up or down based on the second signal. The method includes comparing the credit count against a first threshold. The method includes calculating an average credit count that accounts for the credit count and previous credit counts and comparing the average credit count against a second threshold. The method includes adjusting an activity level of the load circuitry if either threshold is crossed.

Power management circuit with per activity weighting and multiple throttle down thresholds

Described herein are embodiments of an apparatus configured for dynamic link width modulation, a system including an apparatus configured for dynamic link width modulation, a method for dynamic link width modulation, and computer-readable media having instructions that, if executed by one or more processors, cause an apparatus to perform a dynamic link width modulation method. An apparatus configured for dynamic link width modulation may include a first counter for determining a length of a queue of packets at a source of a link, a second counter for determining a rate of utilization of the link, and a power control unit configured to modify a width of the link based at least in part on the length of the queue and the rate of utilization. Other embodiments may be described and/or claimed.

Dynamic link width modulation

A system and method for distributed computing, including executing a job of distributed computing on compute nodes. The speed of parallel tasks of the job executing on the compute nodes are adjusted to increase performance of the job or to lower power consumption of the job, or both, wherein the adjusting is based on imbalances of respective speeds of the parallel tasks.

Adjustment of execution of tasks

A non-transitory computer readable storage medium having stored thereon instructions executable by one or more processors to perform operations including: receiving a plurality of input parameters including (i) a workload type, (ii) a list of selected nodes belonging to a distributed computer system, and (iii) a list of frequencies; responsive to receiving the plurality of workload parameters, retrieving calibration data from a calibration database; generating a power estimate based on the plurality of workload parameters and the calibration data; and providing the power estimate to a resource manager is shown. Alternatively, the input parameters may include (i) a workload type, (ii) a list of selected nodes belonging to a distributed computer system, and (iii) an amount of available power, wherein the estimator may provide an estimation of the frequency at which the nodes should operate to utilize as much of the available power without exceeding the available power.

Methods and apparatus to estimate power performance of a job that runs on multiple nodes of a distributed computer system

Since the maximum power consumption is largely a concern at the power supply domain, a limited number of nodes may be allowed to consume their maximum power consumption by preventing other nodes from consuming their maximum power consumption. This approach may be used either instead of or in cooperation with existing maximum power consumption regulators.

Controlling power consumption in processor-based systems and components thereof

Embodiments help dynamically configure the width of PCIe links and also determine how to best configure the appropriate link width. This helps avoid situations where PCIe links are almost always active even at very low traffic rates. Embodiments achieve these benefits based on, for example, run-time monitoring of bandwidth requirement for integrated and non-integrated ports located downstream for the PCIe controller. This provides power savings with little impact on performance. Other embodiments are discussed herein.

Dynamic link width adjustment

Methods and apparatus for implementing active interconnect link power management using an adaptive low-power link-state entry policy. The power state of an interconnect link or fabric is changed in response to applicable conditions determined by low-power link-state entry policy logic in view of runtime traffic on the interconnect link or fabric. The low-power link-state policy logic may be configured to include consideration of operating system input and Quality of Service (QoS) requirements for applications and devices employing the link or fabric, and device latency tolerance requirements.

Adaptive low-power link-state entry policy for active interconnect link power management

Mechanisms for exposing a protected memory address are provided. A processing device may store a data value at a protected memory address. The protected memory address may be a control register or a status register. The processing device may identify a mirror relationship between the protected memory address and an unprotected memory address and copy the data value from the protected memory address to the unprotected memory address. The unprotected memory address may be directly accessible via an external interface.

Exposing protected memory addresses

An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.

Method and apparatus for optimizing power and latency on a link

Methods and apparatus relating to optimization of performance and/or power consumption during memory power down state are described. In an embodiment, a memory controller may include logic to cause one or more ranks of a DIMM to enter a clock enable slow mode. Other embodiments are also described.

Optimizing performance and power consumption during memory power down state

A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.

Method and system to improve the operations of a registered memory module

Described herein are techniques for dynamic memory frequency/voltage scaling to augment existing memory power management techniques and further improve memory power efficiency. Each operating point is defined as an operational state for the memory.

Memory power management via dynamic memory operation states

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Aloha, OR, United States of America

James W Alexander