Unisys Corporation

James W Adcock

Craig B Johnson

Joseph E Kessler

Kathleen Georgia Elliot

Kenneth L Willis

Robert S Yach

A sparse matrix paging system is provided that dynamically allocates memory resources on demand. In some cases, this is accomplished by dynamically allocating memory resources, preferably only after a page has been requested. Such a sparse matrix paging system may allow a platform with a large linear address space to more efficiently execute on a platform with a smaller linear address space. Preferably, the sparse matrix paging system only indexes those pages that are actually requested and used in the address space on main store pages or backing store pages. Further, the backing store is preferably not involved unless the total address space allocated by the operating system exceeds the available main store pages.

Sparse matrix

A method and system to provide improved operation of a software emulated platform through the use of a relative address translation cache containing a plurality of cache sets. Each address translation contained within the relative address translation cache contains a Base Descriptor Register selection, a relative address limit check, an access privilege check, generation of an absolute address and a real address, and breakpoint discovery.

Method and system for relative address translation

Sparse matrix paging system

A method and apparatus for emulating a high-precision, high-accuracy clock. In one embodiment, two clocks are used in the emulation. The first clock has precision greater than precision of the second clock and accuracy less than accuracy of the second clock. A checkpoint time relative to elapsed cycles of the second clock and a checkpoint cycle count of cycles of the first clock are periodically stored relative to a checkpoint period that lasts for a selected number of cycles of the second clock. A reference cycle rate of the first clock is calculated relative to the cycle rate of the second clock. The current time is determined as a function of the checkpoint time, a number of cycles of the first clock elapsed since storing the most recent checkpoint cycle count, and the reference cycle rate of the first clock.

Emulation of a high-speed, high-stability clock

A method and circuit for compression and decompression of data. For compression, successive units of input data are received in first register and second registers. The contents of the registers are used to address a lookup RAM, and the data stored in the lookup RAM is used to address a dictionary RAM. If output data from the dictionary RAM does not match output data from the first and second registers, a value from a dictionary counter is stored in the lookup RAM. If output data from the dictionary RAM matches output data from the first and second registers, data read from the lookup RAM is fed back for storage in the first register. The data from the first and second registers is provided as compressed output data. For decompression, the compressed data are used to populate another dictionary RAM, which is used to reconstruct the uncompressed data.

Data compression/decompression circuit and method

A procedure, enabled in software, and applied to a cache/disk environment controlled by a host computer operating through a Block Multiplexor Channel Interface and Storage Control Unit, functions to use FIPS 97 and FIPS 60 protocols to execute data transfers between host processors and a plurality of disks whereby simultaneous operations can function with up to 16 disk units. Up to seen I/O requests can be queued on each of the 16 disk units while the system can normally operate in the cache/disk mode. Additionally, the system can operate in the disk-only mode or storethrough mode.

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Stillwater, MN, United States of America

James W Adcock