International Business Machines Corporation

Globalfoundries Inc.

James Vichiconti

Douglas C La Tulipe, Jr

Sampath Purushothaman

George Frederick Walker

Harold John Hovel

Qiang Huang

Xiaoyan Shao

Steven Erik Steen

Ageeth Anke Bol

Devendra K Sadana

Stephen W Bedell

Keith E Fogel

Ying Di Zhang

Jeehwan Kim

Isaac Lauer

Hendrik F Hamann

Robert J Von Gutfeld

Eric Andrew Joseph

Meikei Ieong

Minhua Lu

Anna Wanda Topol

Steven Alan Cordes

Hiroki Nakano

Leathen Shi

Nicholas C M Fuller

Sebastian Ulrich Engelmann

Albert M Young

James Patrick Doyle

James Andrew Lacey

S Jay Chey

Satyavolu S Papa Rao

Matthew J Farinelli

George Gabriel Totir

Ronald Wayne Nunes

Kathryn C Fisher

George Liang-Tai Chiu

Ryan M Martin

Jun Liu

Richard M Ruggiero, Sr

Stephen J Graziano

Daniel Inns

A method to transfer a layer of graphene from one substrate to another substrate is provided. The method includes providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate. The copper foil is removed exposing a surface of the layer of graphene. Next, an oxide bonding enhancement dielectric layer is formed on the exposed surface of the layer of graphene. A second layered structure including a receiver substrate and a dielectric oxide layer is provided. Next, an exposed surface of the dielectric oxide layer is bonded to an exposed surface of the oxide bonding enhancement dielectric layer. The carrier substrate and the adhesive layer are removed exposing the layer of graphene.

Graphene layer transfer

Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

Three-dimensional integrated circuit device fabrication including wafer scale membrane

A donor wafer containing integrated semiconductor device. The donor wafer has a donor wafer membrane portion that has a device layer and a buried insulating layer. The donor wafer membrane portion has a number of integrated semiconductor devices where each integrated semiconductor device within the plurality of semiconductor devices corresponds to a die formed on the donor wafer. The donor wafer membrane portion has a diameter of at least 200 mm. The donor wafer has a crystalline substrate that is substantially removed from an area of the donor wafer membrane portion such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface. The donor wafer further has a support structure attached to regions of the donor wafer that are outside of the donor wafer membrane portion.

Three-dimensional integrated circuit device using a wafer scale membrane

Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.

Super lattice/quantum well nanowires

An fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiOfilm. Portions of the substrate side are selectively coated with a polymer film and etching of uncoated areas removes at least a substantial portion of the crystalline substrate. A plasma etch tool etches a crystalline substrate to within a pre-determined thickness. The silicon portions of the substrate side are etched by exposure to TMAH. After etching, the donor semiconductor wafer is supported by portions of the substrate that were not etched. The supporting structure allows flexing of the donor semiconductor wafer within the etched areas to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

Wafer scale membrane for three-dimensional integrated circuit device fabrication

Alternative additives that can be used in place of isopropyl alcohol in aqueous alkaline etchant solutions for texturing a surface of a single-crystalline silicon substrate are provided. The alternative additives do not have volatile constituents, yet can be used in an aqueous alkaline etchant solution to provide a pyramidal shaped texture surface to the single-crystalline silicon substrate that is exposed to such an etchant solution. Also provided is a method of forming a textured silicon surface. The method includes immersing a single-crystalline silicon substrate into an etchant solution to form a pyramid shaped textured surface on the single-crystalline silicon substrate. The etchant solution includes an alkaline component, silicon (etched into the solution as a bath conditioner) and glycerol or ethylene glycol as an additive. The textured surface of the single-crystalline silicon substrate has (111) faces that are now exposed.

Single-crystalline silicon alkaline texturing with glycerol or ethylene glycol additives

A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

Structure with isotropic silicon recess profile in nanoscale dimensions

In a liquid crystal display device, a method for creating desirable pretilt angle by means of topography of the substrates, such as a surface that is sloped with respect to the surface of the electrodes. In combination with a low pretilt but highly photo-stable alignment layer, which may be very resistant to high levels of ultraviolet radiation, a high pretilt and photo-stable alignment structure is generated, by essentially combining two incompatible technical approaches. The ever more stringent requirements for projection displays are met. The methods for producing such sloped surfaces and the considerations related to design of the sloped surfaces are disclosed.

Method of producing UV stable liquid crystal alignment

A method for layer transfer using a boron-doped silicon germanium (SiGe) layer includes forming a boron-doped SiGe layer on a bulk silicon substrate; forming an upper silicon (Si) layer over the boron-doped SiGe layer; hydrogenating the boron-doped SiGe layer; bonding the upper Si layer to an alternate substrate; and propagating a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate. A system for layer transfer using a boron-doped silicon germanium (SiGe) layer includes a bulk silicon substrate; a boron-doped SiGe layer formed on the bulk silicon substrate, such that the boron-doped SiGe layer is located underneath an upper silicon (Si) layer, wherein the boron-doped SiGe layer is configured to propagate a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate after hydrogenation of the boron-doped SiGe layer; and an alternate substrate bonded to the upper Si layer.

Layer transfer using boron-doped SiGe layer

A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.

Low-cost strained SOI substrate for high-performance CMOS technology

A system and method for measuring thermal distributions of an electronic device during operation is disclosed. The system includes an electronic device, a heat sink adjacent to the electronic device and an electrical-insulating layer disposed on the electronic device so as to separate the electronic device and the heat sink. The system further includes a plurality of thermal sensors located on the electrical-insulating layer, each of the plurality of thermal sensors in a different location. The plurality of thermal sensors is located within one or more thin film circuit layers disposed adjacent to the electrical insulating layer. The system further includes a module for receiving thermal information from the plurality of thermal sensors during operation of the electronic device. The system further includes a processor coupled to the module for generating a thermal distribution of the electronic device based on the thermal information received from the plurality of thermal sensors.

Thermal measurements of electronic devices during operation

A device for preventing unauthorized access to a rotating shaft. More particularly, an apparatus is provided to prevent unintended and unauthorized operation of a rotating shaft by encasing a vulnerable portion of the shaft in a standard pin type lock which renders the shaft impervious to unauthorized operation. It is intended that the rotating shaft cannot be operated unless it is unlocked and a tool is applied to a portion thereof.

Tamper proof set screw

Growing community of inventors

Peekskill, NY, United States of America

James Vichiconti