Altera Corporation

James Tyson

Roger May

Mark Dickinson

Volker Mauer

Andrew Martyn Draper

Colman Cheung

Edward H Flaherty

Andrew Crosland

Stephane Cauneau

Lambertus De Jong

Ray Schouten

Fabio Petrassem De Sousa

In one aspect, a device is configured to provide a lookup operation for looking up a data value stored in a result table. The device includes several data tables for storing keys, or compressed representations of keys, associated with data values stored in the result table. During an example lookup operation, storage locations included within the data tables are searched for a particular key, or compressed representations of the key. If the key is found, the storage location is used to identify a memory address associated with the result table. In some implementations, the data tables are accessed in parallel to provide a lookup operation having a fixed latency. Storage locations within the data tables also are arranged to reduce the amount of memory used to implement each data table. In some implementations, the data tables are configured to use no more than one result table access per lookup operation.

Method and system for an algorithm and circuit for a high performance exact match lookup function

Embodiments of the present invention provide methods of reading data from and writing data to a memory, computer program products for performing such methods, and apparatus for reading data from and writing data to, a memory, which apparatus may be implemented, for example, as a Field Programmable Gate Array (FPGA). A key associated with data to be read from or written to the memory is converted into two separate values, which values are themselves converted into first and second index values, each having an associated signature value. The index values are used as indices to a signature table containing a signature value for each data entry stored in the memory from which data is to be read or to which data is to be written. In a read operation, a signature of the signature table which matches one of the signature values derived from the key is identified and a read address is calculated based on the index value associated with the matching signature value derived from the key. In a write operation, a signature value is written to the signature table at an address corresponding to one of the index values derived from the key, and a write address is calculated based on that index value.

Memory access system

A system includes a packet generator and a packet checker. The packet generator is operable to operable to generate a packet for transmission to a destination device. The packet includes a plurality of fields, including a code field that is operable to store a code generated based on an expected modification to the packet during transmission. The packet checker is associated with the destination device and is operable to receive the packet.

Packet communication testing apparatus and associated methods

Pre-configuration of a programmable device permits implementation and operation of the device using a first, dedicated operation usable upon power up of the programmable device without the need for programming the device using external configuration data. Configuration data can be provided in any suitable manner to re-configure the device to perform a second, programmable operation. The pre-configured design preferably uses programmable resources and leaves dedicated resources undisturbed during both first and second operations.

Functional pre-configuration of a programmable logic device

A receiving device oversamples incoming serial data using multiple phases of its system clock. The device detects an initial edge in the set of samples and selects a sample based on the location of the initial edge. A first bit is set to the value of the selected sample. A portion of the set of samples following the initial edge. If an edge is detected, then a sample is selected based upon the location of the detected edge and the next bit is set to the value of the selected sample. If an edge is not detected within this portion, then the position of the next edge is estimated. A sample is selected based upon the location of the estimated edge and the next bit is set to the value of the selected sample. The analysis is repeated for another portion of the set of samples following the newest edge.

Efficient data recovery algorithm for serial data

A microprocessor-based system includes multiple peripherals, which can be accessed by the microprocessor over a system bus, with the aid of address decoding logic. Depending on the required functionality of the system at any time, one or more of the peripherals can be disabled. When a peripheral device is disabled, the address decoding logic of the system is modified to ensure that no attempts are made to access that peripheral device.

Microprocessor system

A programmable logic device is reconfigurable between two functionalities, while it is in use. The programmable logic device has a first store, into which configuration data may be downloaded from an external memory device, and a second store, in which a copy of the configuration data is maintained, with the functionality of the programmable logic device being determined by the copy of the configuration data, thereby allowing additional configuration data to be downloaded from the external memory device into the first store, while maintaining the functionality of the device. This allows the device to be used to provide two different functionalities, and to be switched between these two functionalities with minimal delay for reconfiguration of the device.

Updating configuration for programmable logic device

A programmable logic device (PLD) includes a transceiver, configurable phase-locked loop (PLL) circuits, and programmable logic circuits. The logic circuits and PLL circuits are programmed to enable the transceiver to flexibly respond to various types of input serial data signals, and to flexibly generate various types of output serial data signals, such as Serial Digital Interface (SDI) signals and High Definition SDI (HD-SDI) signals. This allows the PLD to be used in a wide variety of systems without requiring custom external components.

Programmable logic device with transceiver and reconfigurable PLL

Apparatus and method extract data from a data stream. The method includes oversampling the data stream, performing first processing on adjacent bits of the oversampled data stream, performing second processing the results of the first processing, comparing the results of the second processing, and selecting an alignment of data based on the comparison. The method can be efficiently implemented using accumulators, delay elements, and XOR elements. In this manner, data may be extracted from the data stream despite a varying or unknown phase or duty cycle, or in the presence of jitter.

Method and apparatus for extracting data from an oversampled bit stream

A multiple bus architecture for a system on a chip including bridges for decoupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.

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James Tyson