Intermolecular, Inc.

James Tsung

Rick Endo

Kurt H Weiner

Indranil De

Maosheng Zhao

Tony P Chiang

Jeremy Cheng

Richard Endo

Chen-An Chen

Jay Dedontney

Martin Romero

Timothy Joseph Franklin

Frank Greer

Hong Sheng Yang

Chien-Lan Hsueh

Shouqian Shao

Kent Riley Child

Stephen Charles Garner

Owen Fong

In some embodiments, apparatus are provided that provide for flexible processing in both high productivity combinatorial (HPC) and full wafer modes. The apparatus allow for interchangeable functionality that includes deposition with different sizes of targets, plasma treatment, ion beam treatment, and in-situ metrology. The functional modules are designed so that the modules may be interchanged with minimal effort and reduced system downtime.

Interchangeable sputter gun head

Apparatus for high productivity combinatorial (HPC) processing of semiconductor substrates and HPC methods are described. An apparatus includes a showerhead and two or more pressure-controlled one-way valves connected to the showerhead and used for controlling flow of different processing gases into the showerhead. The pressure-controlled one-way valves are not externally controlled by any control systems. Instead, these valves open and close in response to preset conditions, such as pressure differentials and/or flow differentials. One example of such pressure-controlled one-way valves is a check valve. These valves generally allow the flow only in one direction, i.e., into the showerhead. Furthermore, lack of external controls and specific mechanical designs allow positioning these pressure-controlled one-way valves in close proximity to the showerhead thereby reducing the dead volume between the valves and the showerhead and also operating these valves at high temperatures.

High productivity combinatorial processing using pressure-controlled one-way valves

In some embodiments, apparatus are provided that provide for flexible processing in high productivity combinatorial (HPC) system. The apparatus allow for interchangeable functionality that includes deposition, plasma treatment, ion beam treatment, in-situ annealing, and in-situ metrology. The apparatus are designed so that the functionality may be integrated within a single processing chamber for enhanced flexibility.

Multipurpose combinatorial vapor phase deposition chamber

In some embodiments of the present invention, a shield is provided wherein the shield comprises a ceramic insulation material. The ceramic insulation material fills the space between the shield and the substrate surface and maintains a gap of less than about 2 mm and advantageously, less than about 1 mm. The shield may further be connected to ground through a low-pass filter operable to prevent the loss of high frequency RF power through the shield to ground but allow the dissipation of charge from the shield to ground through a low frequency or DC signal. In some embodiments, the ceramic insulating material further comprises a removable ceramic insert. The ceramic insert may be used to select the size of the aperture. The ceramic insert further comprises a slot operable to isolate the bottom lip of the ceramic insert from the upper portion for a PVD deposition.

Combinatorial RF bias method for PVD

A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate.

Combinatorial process system

A system for processing a semiconductor substrate is provided. The system includes a mainframe having a plurality of modules attached thereto. The modules include processing modules, storage modules, and transport mechanisms. The processing modules may include combinatorial processing modules and conventional processing modules, such as surface preparation, thermal treatment, etch and deposition modules. In one embodiment, at least one of the modules stores multiple masks. The multiple masks enable in-situ variation of spatial location and geometry across a sequence of processes and/or multiple layers of a substrate to be processed in another one of the modules. A method for processing a substrate is also provided.

Method and system for isolated and discretized process sequence integration

The various embodiments of the invention provide for relative movement of the substrate and a process head to access the entire wafer in a minimal space to conduct combinatorial processing on various regions of the substrate. The heads enable site isolated processing within the chamber described and method of using the same are described.

Multi-region processing system

A structure for independently supporting a wafer and a mask in a processing chamber is provided. The structure includes a set of extensions for supporting the wafer and a set of extensions supporting the mask. The set of extensions for the wafer and the set of extensions for the mask enable independent movement of the wafer and the mask. In one embodiment, the extensions are affixed to an annular ring which is capable of moving in a vertical direction within the processing chamber. A processing chamber, a mask, and a method for combinatorially processing a substrate are also provided.

Method and system for mask handling in high productivity chamber

A method of combinatorially processing a substrate and combinatorial processing chamber are provided. The processing chamber includes opposing annular rings defining a conductance gap that extends radially outward. The opposing annular rings are configured to vary the conductance gap in-situ. The variation of the conductance gap is another parameter for processing regions of a substrate differently to evaluate the impact of the conductance variation on a deposition process.

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Milpitas, CA, United States of America

James Tsung