Texas Instruments Corporation

Sun Microsystems, Inc.

James Tran

Tyler J Thorp

Gin S Yee

David J Greenhill

Richard X W Gu

A method for synchronizing a data signal and a clock signal has been developed. The method first generates two separate intermediate data signals. The intermediate data signals lag the input data signal. The separate durations of the two lagging signals are combined to form an output data signal that is synchronized with the system clock signal.

Method for synchronizing clock and data signals

The charge pump, having increased precision over known charge pumps, for a self-biasing phase-locked loop and a self-biasing delay-locked loop is disclosed herein. It includes a p-type charge pump and a n-type charge pump. The charge pump has inputs for an up and a down voltage output from a phase and frequency detector and for at least two bias voltage outputs from a bias generator. The p-type charge pump is coupled to the up output of the phase and frequency detector and a first bias voltage output from the bias generator circuit. The n-type charge pump is coupled to the p-type charge pump and has inputs coupled to the down output of the phase and frequency detector and a second bias voltage output from the bias generator circuit. A first capacitor is coupled across the p-type charge pump. This charge pump operates between 1 &mgr;A to 10 &mgr;A. It is a more balanced design than known charge pump designs. Although PMOS is very slow, the present implementation of both the p-type and the n-type charge pumps pull up and pull down at the same time. This charge pump can be used with very narrow bandwidths. As another advantage, due to the up voltage output of the phase and frequency detector increasing at a rate approximate to current down voltage output, a relatively small amount of phase noise exists. With reference to phase error correction, this charge pump implementation more finely tunes the output signal of the phase locked loop design.

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San Jose, CA, United States of America

James Tran