Medtronic, Inc.

James Thomas May

Larry Earl Tyler

Andreas A Fenner

Paul F Gerrish

Lary R Larson

Daniel E Fulton

James W Bell

A protection for ICs against ESD transients includes a circuit with a master circuit driving a slave circuit. The master circuit responds to ESD voltage V(t). The slave circuit comprises parallel shunt devices having common inputs. The output of the master circuit is coupled to the common inputs. As V(t) increases the master circuit applies a portion of V(t) to the input of the slave circuit shunt devices. The threshold voltage Vtat which the slave circuit shunt devices would otherwise turn on to a lower value Vt' closer to the holding voltage Vh of the shunt devices. All of the slave circuit devices turn on substantially simultaneously at about Vt&#x2032; close to Vh, thereby shunting the ESD transient to ground at a lower value of V(t). The master and slave circuits are inactive during normal IC operation.

Destructive electrical transient protection

An ESD protection circuit protects circuitry internal to an integrated circuit from ESD damage to electrostatic discharge voltages occurring at one or more of the inputs of the integrated circuit while maintaining substantially zero effective capacitance at the inputs. The ESD protection circuit includes a pair of diodes of opposite conductivity coupled between at least one of the inputs of the integrated circuit and an internal node thereof for providing current paths to the operating supply rails when ESD voltages occurring at the input forward bias the diodes. A unity gain amplifier provides feedback between the input and the internal circuit node to maintain a zero voltage difference therebetween whereby the effective capacitance seen at the input is reduced to substantially zero.

Low input capacitance electrostatic discharge protection circuit utilizing feedback

Methods and apparatus for burn-in of integrated circuit (IC) dies at the wafer level. In one embodiment, a wafer is fabricated having an array of dies formed thereon wherein the dies are separated by scribe areas. Surrounding each die is one or more ring conductors which are electrically coupled to various circuits on the die via die bond pads. The wafer further includes a series of conductive pads located in an inactive region of the wafer. Electrically connecting the conductive pads to the ring conductors is a series of redundant scribe conductors. During burn-in, a burn-in indicating apparatus located on each die monitors burn-in parameters such as elapsed burn-in time. The indicating apparatus further records the elapsed burn-in time (or other parameter). The indicating apparatus may be subsequently interrogated to verify the burn-in time.

Method and apparatus for wafer-level burn-in

Electrostatic Discharge (ESD) protection scheme includes a divided rail structure to route damaging ESD away from sensitive circuitry. Specifically, V and V rails are divided to segregate the ESD current within a circuit, thus isolating the sensitive circuitry from ESD exposure. In an exemplary embodiment, V is divided into V -esd and V core, while V is divided into V -esd and V core. The structure in cooperation with diodes, clamps and resistors enables to isolate the rails (V core and V core) associated with sensitive circuitry from ESD current.

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Tempe, AZ, United States of America

James Thomas May