Supertex, Inc.

Microchip Technology Inc.

Amfit, Inc.

Cromemco Inc.

Other

Piradian, Inc.

Analytek, Ltd.

James Terrell Walker

Christopher I Walker

Robert G Lorenz

Jimes Lei

Arjen Sundman

Benedict C K Choy

Kamran K Abadi

Ming-Yuan Yeh

Andrew Read

Tony G Tadin

Marvin L Kausch

Raymond S Larsen

An improved power converter is disclosed.

Power converter with inductance invariance

Systems and methods are disclosed for operating a highly linearized resistance for a switch through use of a bootstrapped features. In one exemplary implementation, there is provided a method and system that implements a method for operating a circuit configured to provide a highly linearized resistance including receiving a signal via a bootstrapped switch, coupling the received signal to a gate if the received signal is high, receiving a signal via a switch control input coupled to a high impedance element. Moreover, the method includes coupling the high impedance element to the gate and turning off the switch via a gate turn off when the gate turn off pulls the gate low.

Bootstrapped switch with a highly linearized resistance

A method and system for extending the power output range of a power converter used for a lighting system is disclosed.

Method and apparatus for extending the power output range of a power converter used for a lighting system

A circuit is disclosed for determining which of a multiplicity of LED strings in an illumination system has a fault. A group of circuits determines the maximum, minimum, midpoint between maximum and minimum, and average voltage of the group of LED string voltages in use, and examines the statistical properties of the LED string voltages. Comparators are used to find the strings which have the highest and lowest operating voltages, and to compare the midpoint and average voltages to determine whether the highest or lowest voltage string is responsible for causing a fault in the illumination system operation. Memory means are used to keep the said determined string turned off to prevent faulty operation.

Circuit for detection and control of LED string operation

A phase shift generation circuit has an edge detector, which outputs a first and a second edge signal. The circuit also has a divide by N circuit, which receives a first clock signal and a group of signals representing a number N, and outputs a second clock signal. The circuit further comprises a pulse counter, which receives the first edge signal and the second clock signal, and outputs a group of signals representing the number of the second clock pulses between occurrences of the first edge signal. The circuit has first and second recycling timers, which output a group of pulses approximating a uniformly spaced group across the time duration of the period of the input pulse. The circuit also comprises at least one flip flop which generates a phase shifted output pulse.

Phase shift generating circuit

An electrostatic sensor device including a first sensor element and a second sensor element; a dielectric substrate material formed in two layers, and a sensing hole which penetrates the dielectric substrate material from its upper surface to its lower surface. The first sensor element is receivable in the sensing hole; and second sensor element includes a first conducting ring disposed on an upper surface of said dielectric substrate and surrounding said sensing hole. The second conducting ring is disposed on a lower surface of the dielectric substrate and surrounds the sensing hole. The first sensor element and the second sensor are capable of producing a variable response when the first sensor element is disposed in the sensing hole.

Electrostatic sensor device and matrix

A circuit for generating a high voltage alternating current to drive a load has a current source having a first terminal and a second terminal. The circuit further has an output terminal and a circuit ground terminal. A first switch will conduct between the first terminal of the current source and the circuit ground terminal when the first switch is closed. A second switch will conduct between the first terminal of the current source and the output terminal when the second switch is closed. A third switch will conduct between the second terminal of the current source and the circuit ground terminal when the third switch is closed. A fourth switch will conduct between the second terminal of the current source and the output terminal when the fourth switch is closed. A load is coupled to the output terminal and the circuit ground terminal.

Current driven bipolar high voltage driver for capacitive loads

A switched current source has a first voltage source, a second voltage source, and a third voltage source. A first transistor has a drain terminal coupled to one terminal of a load and a source terminal coupled to the third voltage source. A second transistor has drain, gate and source terminals. The drain terminal of the second transistor is coupled to the gate terminal of the first transistor. The source terminal of the second transistor is coupled to the source terminal of the first transistor. The gate terminal of the second transistor is coupled to the first voltage source. A third transistor has drain, gate and source terminals. The drain terminal of the third transistor is coupled to the gate terminal of the first transistor. The source terminal of the third transistor is coupled to the second voltage source. The gate terminal of the third transistor is coupled to the first voltage source.

MOSFET transistor amplifier with controlled output current

A high speed logic signal level shifter is comprised of: a logic signal buffer for receiving logic signal information and having true and complement state differential outputs; a binary flip-flop circuit with set and reset inputs; a first coupling capacitor connected from the true buffer output to the set input of the binary flip-flop circuit; and a second coupling capacitor connected from the complement buffer output to the reset input of the binary flip-flop circuit. The high speed logic signal level shifter transfers a fast logic signal across a high voltage difference by making use of rapid voltage changes transmitted through small capacitors. The signal changes carried by the capacitors are about 10 times faster than any expected voltage transient on VPP or VNN. Furthermore, the differential coupling circuit is used to provide enhanced protection against undesired circuit switching during supply voltage changes.

High-speed logic signal level shifter

A level translator has an inverter comprising a first transistor having a first predetermined voltage threshold and a second transistor having a second predetermined voltage threshold. The two transistors have control gates being of complementary conductivity. A first capacitor is connected at one end to the gate of the first transistor and at a second end to an input signal. A second capacitor is connected at one end to the gate of the second transistor, the input signal being applied to a second end of the second capacitor. A comparator is used for detecting the relationship between the input signal and a reference voltage. A first current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the first transistor. A second current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the second transistor. A first clamp circuit is used for limiting a gate voltage of said first transistor. A second clamp circuit is used for limiting a gate voltage of said second transistor.

Fast DC coupled level translator

A level translator has a pair of transistors, wherein a first transistor of the pair of transistors and a second transistor of the pair of transistors are complimentary. A pair of capacitors are provided, wherein a first capacitor of the pair of capacitors is coupled to a voltage input VIN and to a gate of a first transistor of the pair of complimentary transistors and a second capacitor of the pair of capacitors is coupled the voltage input VIN and to a gate of a second transistor of the pair of complimentary transistors. A flip flop device is provided having a first input coupled to a drain of the first transistor, and a second input coupled to a drain of the second transistor. A pair of resistors is provided, wherein a first resistor of the pair of resistors is coupled to the gate of the first transistor and to a voltage supply of VDD, and a second resistor of the pair of resistors is coupled to the gate of the second transistor and to a voltage supply VSS. A pair of clamping circuits is provided, wherein a first clamping circuit of the pair of clamping circuits is coupled to the gate of the first transistor and to a voltage supply of VDD, and a second clamping circuit of the pair of clamping circuits is coupled to the gate of the second transistor and to a voltage supply VSS.

Fast AC coupled level translator

A circuit for transmitting logic signals across a high voltage barrier has a logic signal buffer with true and complement state differential outputs. A binary flip-flop with set and reset inputs is further provided. A first coupling capacitor is coupled to the true buffer output and to the set input of the binary flip-flop. A second coupling capacitor is coupled to the complement buffer output and to the reset input of the binary flip-flop circuit.

High speed logic level shifter

A system for electrostatically measuring the shape or pattern of objects including an array of sensor devices having the capability of responding, due to variable electrostatic coupling, to produce differentiated output signals when a sensor element forming part of each device is present and when it is not.

An apparatus is provided for processing a wide dynamic range analog signal which comprises multiple components such as a signal with an in-phase component and a quadrature-phase component in for example separate I and Q data channels, wherein each channel has a dynamic range compressor stage and an operator stage which processes the compressed signals. Optionally the apparatus has a dynamic range expander stage following the operator stage. A method according to the invention involves processing I and Q information after first independently compressing the dynamic range of the signal according to a logarithmic transfer characteristic over a frequency range of interest. A mathematical operation through a F(i,q) function (corresponding to the operator stage) is performed on the compressed components, thereby producing normalized components. The operating transfer function F(i,q) cross links the data channels to effect normalization based on amplitude of information in each of the channels. Dynamic range expansion provides expanded components in an expanded domain. The invention is applicable to any analog signal system having a plurality of channels carrying related signal information.

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Palo Alto, CA, United States of America

James Terrell Walker