Texas Instruments Corporation

James Teng

Cetin Kaya

Qiong M Li

Claus Niels Neesgaard

Lars Risbo

Dale J Skelton

Lieyi Fang

Michael Joseph Tsecouras

Jeff Berwick

Shifeng Zhao

Two transistors of a class D output stage are driven by complementary, variable duty cycle signals PWM+ and PWM&#x2212;. When the pulse width of the PWM+ signal becomes too narrow for reliable operation of prior art over-current protection circuits sensing the drain to source voltage of FETdriven by PWM+, a Narrow Pulse Detector generates a signal indicative of this narrow pulse condition. A Negative Current Sense circuit measures the drain to source voltage across FETduring the much longer conduction time of FETdriven by PWM&#x2212;. Because of the energy stored in the series inductor coupled to the output of the class D stage, a negative current flows through this FETduring its conduction time. The resulting drain to source voltage of FETis measured and compared to a threshold. If the voltage indicative of current is over the threshold, and the Narrow Pulse Detector output indicates a narrow pulse condition, then an inhibit signal is generated which reduces current. A second Negative Current Sense circuit is utilized to similarly detect over-current conditions when the pulse width of PWM&#x2212; becomes too narrow for reliable operation of prior art over-current protection circuits, thus protecting both FETs in the class D output stage from excessive current.

Over-current sensing during narrow gate drive operation of class D output stages

A circuit and method for determining overcurrent in a FET detects an output voltage of the FET in both a positive and negative polarity. The related positive or negative currents through the FET can be measured to determine whether an overcurrent condition exists. By measuring positive and negative currents in the FET, the overcurrent detector can obtain twice as much information as when measuring a positive current alone, and can respond more readily to overcurrent conditions. The overcurrent detector avoids the constraints typically observed in cycle-by-cycle PWM control with single polarity Vds sensing, while permitting a relaxation in the timing requirements for current sensing. A spike suppression circuit also contributes to longer sensing intervals.

Transistor overcurrent detection circuit with improved response time

A system and method is provided for providing integrated over-current protection in a switching power supply. In one embodiment, a switching power supply could comprise a gate drive circuit operative to receive a pulse-width modulated (PWM) signal and to drive at least one power field effect transistor (FET) between alternating activated and deactivated states based on a pulse-width of the PWM signal. The switching power supply could also comprise a current sense circuit operative to measure a current associated with the at least one power FET during the activated state. The switching power supply could also comprise a first over-current protection circuit providing a first adjustment to the PWM signal in response to the current being substantially between a first threshold and a second threshold. The second threshold could be greater than the first threshold. The switching power supply could further comprise a second over-current protection circuit providing a second adjustment to the PWM signal in response to the current being substantially greater than the second threshold.

Systems and methods for providing over-current protection in a switching power supply

A system and method is provided for detecting an over-current condition in a power field-effect transistor (FET). In one embodiment, an over-current detection circuit for detecting an over-current condition in a power FET comprises a current generator circuit operative to generate a reference current and a plurality of matched FETs operative to receive the reference current and provide a reference voltage, the matched FETs being matched to each other and to the power FET. The over-current detection circuit also comprises a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded the reference voltage.

Over-current detection for a power field-effect transistor (FET)

A class AD audio amplifier system () with DC output detection logic () is disclosed. The amplifier system () includes multiple audio channels (), each of which includes a pulse-width-modulator (PWM) (). The DC detection logic () includes a sigma-delta modulator () and a digital low-pass filter () that monitors the PWM output signals from the PWM modulators (). The sigma-delta modulator () operates at a first clock frequency, while the low-pass filter () operates at a much lower clock frequency, so that AC audio components, PWM harmonics, and sigma-delta quantization error is suppressed from the DC detection. The modulated filtered signal is compared against a threshold level (THRSH) to determine whether the amplitude of a DC component at the PWM output is sufficiently high to constitute a fault. If so, a fault detection signal (DC_DET) is issued, and the PWM modulators () are disabled to prevent unsafe conditions in the system ().

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Dallas, TX, United States of America

James Teng