Exar Corporation

Mitsubishi Denki Kabushiki Kaisha

James T Sundby

Alexei N Shkidt

A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods.

Means to reduce the PLL phase bump caused by a missing clock pulse

A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop.

Means to detect a missing pulse and reduce the associated PLL phase bump

An accurate and stable low voltage detect circuit that provides a low voltage detect signal with minimal variation over process and temperature without trimming requirements. The power supply voltage is divided by a resistor voltage divider and compared to the output voltage of a bandgap reference circuit at the inputs of a comparator. The output of the comparator indicates power-on when the voltage divided power supply raises above the bandgap reference voltage. The low voltage detect circuit of the present invention will generate a correct low voltage detect signal even at power supply voltages too low for much of the rest of the circuit to operate properly. At low enough Vcc voltages, a transistor switch disconnects the resistor voltage divider from Vcc, causing all voltages taps off of the resistor voltage divider to drop to ground. Additionally, especially designed bandgap reference and comparator circuits ensure proper operation of the low voltage detect circuit at low power supply voltages.

Accurate low voltage detect circuit

A circuit for switching the well in a CMOS circuit to one of two power supply rails. In, for example, an N-well CMOS process, when an output is driven by a PMOS pull-up transistor, the P+ (drain of the PMOS) to N-well junction may be forward biased if the rail drops to ground. This will cause the output to be pulled to ground. The switching circuit of the present invention avoids the grounding of the output by automatically switching the N-well to the higher power supply rail so that grounding the rail would not cause the output to fall. MOS switches connect the well to either of the power supplies. Therefore, there is no voltage drop from the power supply to the well as in the case of switching circuits using diodes. Also, this circuit connects the well to the highest power supply regardless of which power supply drops to ground. Therefore, it does not require one power supply to be always on for proper operation. A similar P-well design of the switching circuit would provide the same protection for an output drive circuit with an NMOS pull-down transistor.

CMOS well switching circuit

A CMOS opamp having large sinking and sourcing currents, and capable of driving high capacitive loads. The CMOS opamp improves a prior art OPAMP that includes a folded cascode gain stage and a class A/B output stage. By inserting a source follower stage between the folded cascode stage and the output stage, the opamp can drive very large capacitive loads that can also compensate the opamp. By further modifying the output stage, the ability to sink load current is vastly improved.

CMOS opamp with large sinking and sourcing currents and high slew rate

A bandgap circuit for generating an accurate and stable reference voltage at low power supply voltages. Stacking of bipolar devices allows for a lower opamp closed-loop gain, which in turn reduces the error voltage contribution to the output due to opamp offset. A CMOS opamp having NMOS input reference transistors coupled with a new bandgap architecture allows a 1.2 v reference (unlike other stacked architectures) without sacrificing low voltage operation. A new trimming method provides for very efficient trimming of bandgap output voltage. Instead of fine tuning the output voltage by trimming ratioed resistors, the output voltage is trimmed by either changing the area of ratioed bipolar transistors, or changing the magnitude of ratioed currents in equally sized bipolar transistors. Therefore, very fine trimming resolution is possible because of the logarithmic function defining the current or transistor size ratios. A new curvature correction method reduces curvature without requiring additional circuitry. Curvature can be drastically reduced by using resistors with negative temperature coefficient.

Low voltage CMOS bandgap with new trimming and curvature correction

A rail-to-rail CMOS operational amplifier with a large source current and small quiescent current. The CMOS opamp includes a folded cascode input structure, a negative slew detector and an output stage that acts as a push-pull output stage during slewing and a Class A output stage during small signal operation. The opamp can drive large capacitive loads (in excess of 0.5 .mu.F), with the load capacitor providing for the opamp frequency compensation.

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Tracy, CA, United States of America

James T Sundby