Bell Telephone Laboratories

Western Electric Company, Inc.

American Telephone & Telegraph Co., At&t Bell Laboratories

James T Nelson

Charles Walter Pearce

Howard C Kirsch

James H Stefany

James T Clemens

Robert C Sun

Dinesh A Mehta

Glen T Cheney

A self-aligned one transistor-capacitor memory cell is provided which uses an n-channel MOS transistor having separate drain and source regions with a first level polysilicon conductor coupled to the top plate of the capacitor and separate second level polysilicon conductors coupled to the gate and drain of the transistor. A reduction in a dimension of the memory cell is acheived compared to a similar memory cell which uses only one level of conductors.

Dual level polysilicon single transistor-capacitor memory array

In a dynamic MOS (Metal Oxide Semiconductor) random access memory, reverse bias leakage currents which deplete stored charges are reduced by minimizing minority carrier generation-type currents. By so minimizing these currents, the leakage currents become dominated by minority carrier diffusion currents. The memory is ideally formed in an upper semiconductor layer (14) of a layered structure (11). The semiconductor layer (14) is grown epitaxially with a relatively low dopant concentration on a semiconductor substrate (12) with a dopant concentration of the same conductivity type and about three orders of magnitude greater than that of the epitaxially grown layer. The epitaxially grown structure is advantageously suited for the memory circuits in that it may be formed with very low leakage currents. The material further offers by its layered structure a basis for optimizing dynamic memory device characteristics.

MOS Dynamic memory in a diffusion current limited semiconductor structure

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Coopersburg, PA, United States of America

James T Nelson