International Business Machines Corporation

James T Moyer

Stefan P Jackowski

Richard Allen Kelley

Douglas R Chisholm

Wan Lin Leung

Gerald H Miracle

Mark J Wolski

Richard A Neuner

David N Gooding

Mark C Snedaker

Robert G Iseminger

Peter N James

James W Plant

Richard L Hester

Robert G Rush

Gregory S Ulsh

Maurice E Carey

In a data processing system in which an extender unit interconnects the parallel bus of a control unit and a serial link of an extender channel, the channel and the extender unit send and receive serial frames that permit the extender unit to operate under the protocol of the parallel bus with either byte mode devices or non-byte mode devices. The control unit can be modified to operate with a byte mode device in data streaming, a high speed data transfer mode.

Method and apparatus for supporting byte-mode devices and non-byte-mode

A system structured to transfer control information between an IFA (I/O interface adapter) and an I/O processor, and I/O data between an IFA and a CDB (channel data buffer) has separate interfaces for these transfers. The control interface includes a multi-mode, bidirectional control data bus, a control mode bus for establishing the mode of the bus, and a check interface on which the IFA provides error information. The data interface includes a multi-mode, bidirectional data transfer bus, respective SYNC and ACCEPT lines for transferring time-phased control signals to establish the mode of the data transfer bus, and a parity line to indicate to the IFA the parity of the SYNC and ACCEPT lines.

Multimode data system for transferring control and data information in

In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an 'SPD' bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an 'adapter' bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The IOIC comprises at least one shared DMA facility for executing DMA read/write storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for holding control information and data to be transmitted between the SC and one of the IOP's. This enables the SPD bus to be released for utilization by otehr IOP's connected thereto during periods of 'storage latency' that occur after a DMA storage operation has been initiated by one IOP.

Method and apparatus for increasing system throughput via an

A failure detection apparatus detects the existence of an abnormal circuit condition in a circuit which causes a subsequently transmitted data byte to be transmitted from one integrated circuit to another integrated circuit out of sequence relative to a previously transmitted data byte. Even and odd data bytes are received by the first integrated circuit with odd parity. However, the even data byte is transmitted from the first integrated circuit to the second integrated circuit, along existing interface lines extending between the integrated circuits, with odd parity. The parity bit of the odd data byte is inverted, the odd data byte being transmitted along the existing interface lines with even parity. An exclusive OR gate in the second integrated circuit receives the parity bit of the even data byte and passes the parity bit without inversion in response to a first state of a clock signal from an odd latch; however, the exclusive OR gate, upon receipt of the odd data byte, re-inverts the parity bit of the odd data byte in response to a second state of the clock signal. A parity checker compares the data bits of the incoming even and odd data bytes with the parity bit generated by the exclusive OR gate and generates an error check signal representative of the receipt of the subsequently transmitted data byte transmitted out of sequence relative to the previously transmitted data byte when the combined parity of the data bits and parity bit at the input of the parity checker is not odd.

Failure detection method and apparatus

Interface lines interconnect a first circuit to a second circuit. When an abnormal circuit condition affects the interface lines, such as an open circuit or a short circuit condition, the operation of the first and second circuit is detrimentally affected. This invention determines the existence of abnormal circuit conditions in one or more lines of a group of interface lines without using redundant duplex lines. The interface lines are subdivided into a first group, which are used when the apparatus of the present invention is being used to locate abnormal circuit conditions, and a second group, which are not used when the apparatus of the present invention is being used to locate abnormal circuit conditions. Each line of the first group is connected, at its input side, to a corresponding input terminal of a first exclusive-or gate and, at its output side, to a corresponding input terminal of a second exclusive-or gate. The first and second exclusive-or gates are input to a matching circuit, an output signal from the matching circuit indicating the existence of an abnormal circuit condition in the first group of lines. One line of the first group is connected to an input side of the second group. The output side of the second group is connected to an additional input terminal of the second exclusive-or gate. An output signal from the matching circuit indicates the existence of an abnormal circuit condition in at least one line of either one or both of the first and second group of lines.

Interface checking apparatus

Channel data buffer apparatus for buffering data being transferred between an input/output channel unit and a main storage unit in a digital data processing system. In the disclosed embodiment, data is generally transferred between the channel unit and the data buffer (a 'channel/buffer' transfer) in two-byte segments and between the main storage unit and the data buffer (a 'storage/buffer' transfer) in eight-byte segments. The data buffer is comprised of eight column-forming byte-wide multirow storage arrays each having its own address mechanism for accessing any desired row therein. Corresponding rows in the different storage arrays provide the corresponding eight-byte rows for the data buffer as a whole. For storage/buffer transfers, data buffer address circuitry is provided for enabling a group of eight contiguous bytes to be read out of or written into the data buffer on a single access even though some of the bytes may be located on one row of the data buffer and other of the bytes on the next row of the data buffer. For channel/buffer transfers, data buffer address circuitry is provided for enabling a group of two contiguous bytes to be read out of or written into the data buffer on a single access even though one of the bytes may be located on one row of the data buffer and the other of the bytes on the next row of the data buffer. For storage/buffer transfers, an eight-byte wrap-around data shifter is located between the data buffer and the main storage unit for enabling any necessary alignment or realignment of the data being transferred. These features enable data to be loaded into the data buffer in a packed manner and without regard to the storage word boundary alignments in the main storage unit. Among other things, this minimizes the hardware needed for buffering the data and improves the data chaining capability of the system.

Channel data buffer apparatus for a digital data processing system

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Endwell, NY, United States of America

James T Moyer