Intel Corporation

Dialog Semiconductor (uk) Limited

Other

Intle Corporation

James T Doyle

Carl F Liepold

Malay Trivedi

Ambreesh Bhattad

Kevin Yi Cheng Chang

Milan Dragojevic

Erik Mentze

Horst Knoedgen

Nicholas D Triantafillou

Brent D Thomas

Erik A McShane

Ibiyemi Omole

Steven P Hardy

Jonathon Stiff

Hormuzd M Khosravi

Eliezer Tamir

Men Long

Robert W Strong

Edward John Bawolek

Lokpraveen B Mosur

Paritosh Saxena

Simoni Ben-Michael

Paul J Thadikaran

Akshay Ramesh Kadam

Paul S Schmitz

Edward J Pullin

Syed R Naqvi

James P Smith

Udbhava A Shrivastava

Tim Beatty

Richard J Heiler

Rose Wang

Mark J Kachmarek

Fuding Ge

Qing Li

Xiaoying Yu

Yong-Bin Kim

Aysel Yildiz

Brad W Stewart

Carol L Barrett

Jiang William

The present document relates to power converters. A power converter may be configured to convert an input voltage at an input of the power converter into an output voltage at an output of the power converter. The power converter may comprise a first switching circuit with a first inductor, a first high-side switching element, and a first low-side switching element. The power converter may comprise a second switching circuit with a second inductor, a second high-side switching element, and a second low-side switching element. The power converter may comprise a capacitive element having a first terminal coupled to the first high-side switching element and to the second high-side switching element and having a second terminal coupled to the first low-side switching element at a first node. The power converter may comprise a third switching element coupled between the first node and the output of the power converter.

Multi-mode two-phase buck converter

The present document describes a power converter configured to provide energy at an output based on energy provided at an input. The power converter comprises a first switch, wherein a first node is coupled to the input and wherein a second node is coupled to an intermediate point, a second switch, wherein a first node is coupled to the intermediate point and wherein a second node is coupled to an inductor point, a capacitor, wherein a first node of the capacitor is coupled to the intermediate point, a first diode element, wherein a first node is coupled to a second node of the capacitor and wherein a second node is coupled to the inductor point, a second diode element, wherein a first node is coupled to a reference port, and wherein a second node is coupled to the second node of the capacitor; and an inductor, wherein a first node is coupled to the inductor point and wherein a second node is coupled to the output.

Power converter with a high conversion ratio

A multi-phase switching power converter includes a panic mode detector that triggers the activation of each phase in an open-loop mode of operation in which an open-loop duty cycle is used that is greater than a closed-loop duty cycle used during closed-loop operation for the active phases.

Multi-phase DC-DC converters with open-loop PWM for transient performance enhancement

A two-stage multi-phase switching power converter operates its first stage during nominal operation responsive to a nominal clocking frequency and operates its second stage during the nominal operation responsive to a second-stage clocking frequency that is greater than the nominal clocking frequency. In response to an application of a load, the first stage temporarily increases its clocking frequency from the nominal clocking frequency and implements a fixed duty cycle.

Two-stage multi-phase switch-mode power converter with inter-stage phase shedding control

In one or more embodiments, a method comprises comparing an output voltage for a multi-phase DC-DC switching power converter to a reference voltage to produce an error voltage. The method further comprises, for a first inductor, generating a first dual-ramp voltage signal having a first DC voltage level, and level-shifting the first dual-ramp voltage signal to form a second dual-ramp voltage signal having a second DC voltage level different from the first DC voltage level. Further, the method comprises switching on a first power switch coupled to the first inductor according to a duty cycle determined responsive to a comparison of the second dual-ramp voltage signal to the error voltage, where the level-shifting of the first dual-ramp voltage signal adjusts the duty cycle of the first power switch to balance a current in the first inductor with a current in a second inductor for the multi-phase DC-DC switching power converter.

Dual-edge pulse width modulation for multiphase switching power converters with current balancing

A circuit and a method for power conversion and for generating an output voltage in accordance with a reference voltage are presented. The power converter has a circuit for filtering the output voltage, an error amplifier circuit that compares the reference voltage and the filtered output voltage for generating an error voltage as a result of the comparison. There is a circuit for driving one or more switching devices in dependence on the error voltage. The error amplifier circuit has a first differential circuit and a first bias current generation circuit for generating a first bias current for the first differential circuit, a second differential circuit and a second bias current generation circuit for generating a second bias current for the second differential circuit, and a circuit for redistributing the first bias current to the second differential circuit or redistributing the second bias current to the first differential circuit.

Adaptive amplification active filter for divider-less high frequency DC-DC converters

Techniques for a data storage device to locally implement security management functionality. In an embodiment, a security management process of the data storage device is to determine whether an access to non-volatile media of the data storage device is authorized. In certain embodiments, the data storage device is to restrict access to a secure region of the non-volatile storage media, the secure region to store information used and/or generated by a security management process of the data storage device.

Techniques for security management provisioning at a data storage device

In some embodiments, a multi-phase converter with dynamic phase adjustment is provided. In some embodiments, a controller may include circuitry to control how many phase legs are active based on output current and also which phase legs are to be enabled.

Dynamically adjusted multi-phase regulator

In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.

High speed voltage regulator with integrated loseless current sensing

Inductors packaged with a voltage regulator for an integrated circuit within the same package are deposited to a sufficient thickness to reduce resistance and improve the quality factor. Furthermore, the voltage regulator switches currents through the inductors at a relatively high frequency such that the overall size and inductances of the inductors may be reduced. As a consequence, integrating both the integrated circuits including a voltage regulator and associated inductor array in a single package is facilitated. Other embodiments are described and claimed.

Packaged voltage regulator and inductor array

Methods and systems to amplify and convert a single-ended analog signal to a differential signal and to convert the differential signal to a digital value, including to time-multiplex a plurality of windowed single-ended analog error signals, amplify a difference between the time-multiplexed analog signals, sample a corresponding amplified difference signal and an inverted amplified difference signal, amplify and center the samples about a common mode, and convert a corresponding amplified differential signal to digital values in a pipeline fashion. Bias adjustable features may be implemented to control a bandwidth, and clock rates may be adjustable to correspond to the bandwidth.

Single-ended to differential amplification and pipeline analog-to-digital conversion for digitally controlled DC-DC converters

An apparatus includes a memory buffer, a first signal buffer, a locked loop circuit and a feedback circuit. The memory buffer provides a data signal to an output terminal of the memory buffer in response to a first clock signal. The first signal buffer is coupled between the output terminal of the memory buffer and a data line of a bus. The first signal buffer introduces a first delay. The locked loop circuit furnishes the first clock signal to establish a predefined relationship between a phase of a second clock signal and a phase of a third clock signal. The feedback circuit produces the second clock signal in response to the first clock signal. The feedback circuit includes a second signal buffer to introduce a second delay to the second clock, and the second delay is approximately the same as the first delay that is introduced by the first signal buffer.

Clocking architecture to compensate a delay introduced by a signal buffer

A system includes a transmission line, a driver, a load, a compensation capacitor and a compensation resistor. An output terminal of the driver is coupled to one end of the transmission line, and the load is coupled to the other end of the transmission line. The compensation capacitor is coupled in parallel with the output terminal of the driver, and the compensation resistor is coupled in series between the other end of the transmission line and the load.

Technique and apparatus for terminating a transmission line

A sub-bandgap reference circuit yielding a reference voltage smaller than the bandgap voltage of silicon. The circuit generates a negative temperature coefficient signal V,and an oppositely tracking (positive temperature coefficient) &Dgr;V,, and takes the average of two signals related to &Dgr;V,-V,to yield a temperature-compensated voltage of one-half the bandgap voltage of silicon. The circuit features an unequal area current mirror feeding the diodes and resistors used to generate the &Dgr;V,-V,signals using low supply voltages (less than 1.5 volts). A standard CMOS implementation provides low power consumption at a supply voltage of only 1 volt with a good temperature coefficient. The averaging circuit may be implemented by a continuous time divider or by using switched capacitor techniques. The loop amplifier used in the &Dgr;V,-V,circuitry operates with low headroom in part due to a n-well biasing scheme that lowers the effective threshold voltage of the p-channel FETs used in the loop amplifier.

Low supply voltage sub-bandgap reference circuit

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Chandler, AZ, United States of America

James T Doyle