Lsi Corporation

Intel Corporation

Lucent Technologies Inc.

Other

Agere Systems Inc.

Agere Systems Guardian Corp.

James T Clee

Deepak Mital

Jerry Pirog

Te Khac Ma

Tsung-Yuan Charles Tai

Ren Wang

Andrew J Herdrich

Debra Bernstein

Jr-Shian Tsai

David Sonnier

Stephen R Van Doren

William G Burroughs

Niall D McDonnell

Hugh Wilkinson

Yipeng Wang

Andrew Cunningham

Bruce Richardson

Narender R Vangati

Joseph R Hasting

Gage Eads

Jonathan Kenny

Stephen Miller

An Yan

Jamison D Whitesell

Edwin Verplanke

Bradley A Burres

Namakkal N Venkatesan

Steven J Pollock

Kevin Joseph Lynch

Raul A Aguilar

James Edward Guziak

Walter G Soto

Bernard Lee Morris

Robert J Munoz

Farrukh Amjad Latif

James Guziak

Eugene Joseph Yurek

Yi Liang

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ('LLC'), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

Multi-core communication acceleration using hardware queue device

Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

Technologies for a distributed hardware queue manager

Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A scheduler generates contexts corresponding to tasks received by the packet classification processor from corresponding processing modules, each context corresponding to a given flow, and stores each context in a corresponding per-flow first-in, first-out buffer of the scheduler. A packet modifier generates a modified packet based on threads of instructions, each thread of instructions corresponding to a context received from the scheduler. The modified packet is generated before queuing the packet for transmission as an output packet of the network processor, and the packet modifier processes instructions for generating the modified packet in the order in which the contexts were generated for each flow, without head-of-line blocking between flows. The modified packets are queued for transmission as an output packet of the network processor.

Modifying data streams without reordering in a multi-thread, multi-flow network processor

Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A packet classification processor determines, independent of a flow identifier of the received task, control data corresponding to each task. A multi-thread instruction engine processes threads of instructions corresponding to received tasks, each task corresponding to a packet flow of the network processor and maintains a thread status table and a sequence counter for each flow. Active threads are tracked by the thread status table, and each status entry includes a sequence value and a flow value identifying the flow. Each sequence counter generates a sequence value for each thread by incrementing the sequence counter each time processing of a thread for the associated flow is started, and decrementing the sequence counter each time a thread for the associated flow is completed.

Changing a flow identifier of a packet in a multi-thread, multi-flow network processor

Described embodiments provide a packet assembler for a network processor. The network processor includes a plurality of processing modules for processing received packets into one or more processed-packet portions. A shared system memory of the network processor receives processed-packet portions corresponding to packet assemblies. Each of the packet assemblies has associated tasks. A packet assembly processor constructs an output packet for each packet assembly from the processed-packet portions in accordance with instructions from the tasks associated with the packet assembly. The packet assembly processor coordinates storage of the processed-packet portions for each output packet that is read from the system memory based on the instructions from the tasks associated with the corresponding packet assembly.

Packet assembly module for multi-core, multi-thread network processors

Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler. A thread status manager maintains a thread status table having N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, and a thread indicator. A sequence counter generates a sequence value for each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed, by the multi-thread instruction engine. Instructions are processed by the multi-thread instruction engine in the order in which the threads were started.

Thread synchronization in a multi-thread network communications processor architecture

Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from processing modules of the network processor. The packet classifier processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler, and each thread associated with a data flow. A thread status table has N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, a thread indicator and a flow indicator. A sequence counter generates a sequence value for each data flow of each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed. Instructions are processed in the order in which the threads were started for each data flow.

Thread synchronization in a multi-thread, multi-flow network communications processor architecture

Described embodiments provide for processing received data packets into packet reassemblies for transmission as output packets of a network processor. A packet assembler determines an associated packet reassembly of data portions and enqueues an identifier for each data portion in an input queue corresponding to the packet reassembly associated with the data portion. A state data entry corresponding to each packet reassembly identifies whether the packet reassembly is actively processed by the packet assembler. Iteratively, until an eligible data portion is selected, the packet assembler selects a given data portion from a non-empty input queue for processing and determines if the selected data portion corresponds to a reassembly that is actively processed. If the reassembly is active, the packet assembler sets the selected data portion as ineligible for selection. Otherwise, the packet assembler selects the data portion for processing and modifies the packet reassembly based on the selected data portion.

Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate a thread of contexts for each task received by the packet classifier from a plurality of processing modules of the network processor. The scheduler includes one or more output queues to temporarily store contexts. Each thread corresponds to an order of instructions applied to the corresponding packet, and includes an identifier of a corresponding one of the output queues. The scheduler sends the contexts to a multi-thread instruction engine that processes the threads. An arbiter selects one of the output queues in order to provide output packets to the multi-thread instruction engine, the output packets associated with a corresponding thread of contexts. Each output queue transmits output packets corresponding to a given thread contiguously in the order in which the threads started.

Thread synchronization in a multi-thread network communications processor  architecture

A bi-directional buffer includes the capability to turn the current mirror off when the bi-directional buffer is in the receive mode and quickly turn the current mirror on when the bi-directional buffer goes into the transmit mode. This is accomplished in part by a pair of switches included in the current mirror, which are controlled by enable signals. The switches are configured such that the output transistor of the current mirror is turned on when the bi-directional buffer is in the transmit mode, and turned off when the bi-directional buffer is in the receive mode. Further, a pull up circuit may be added to the current mirror to more quickly bring the gate of the output transistor of the current mirror to its conduction threshold voltage.

Reduced power consumption bi-directional buffer

An apparatus and method which provide increased data flow through a compute platform by optimizing data flow between an external device and the internal circuitry without the need for user intervention. A port router is provided which includes a controller switch, a port switch, and one or more connections between the controller switch and the port switch. The controller switch, the port switch and the one or more connections are adapted to provide dynamic re-routing of connections between the port switch inputs and the controller switch outputs. A method is also provided for dynamically routing ports to internal circuitry of a compute platform. The method includes providing a configurable switching circuit, querying the configurable switching circuit to determine a default topology, computing an optimized topology upon the occurrence of a change of the data flow through the configurable switching circuit, suspending operation and effecting re-routing between the interface ports and the internal circuitry based on the optimized topology, and resuming IO operations through the configurable switching circuit. The method and apparatus may be applied to personal computer systems, information appliances, set-top boxes, cable modems, game consoles, smart appliances, handheld computers, palm-sized computers, embedded control systems, workstations, servers and the like.

Port router

An IO controller device and method for controlling data flow, the method including determining a desired configuration for the IO controller, reprogramming the IO controller to allow for processing of one or more descriptor lists, modifying the configuration of the IO controller to reflect the addition or deletion of one or more virtual controllers, re-enumerating the IO controller, and processing a descriptor list for each of the IO controller and the one or more virtual controllers. The integrated circuit device for use as an IO controller includes a system bus interface, a programmable list processor and a port router. The integrated circuit device is adapted for reconfiguration to add or delete one or more virtual controllers. The virtual controllers provide substantially the full bandwidth supported by the integrated circuit device. The IO controller device and apparatus may be applied to personal computer systems, information appliances, set-top boxes, cable modems, game consoles, smart appliances, handheld computers, palm-sized computers, embedded control systems, workstations, servers and the like.

Method and device for controlling data flow through an IO controller

A system which utilizes a control interface of a powered component of a device to protect said component from being corrupted by random values which may be present on the control interface as a result of powering off or powering on an attached device component. When the powered component powers off the attached component, the powered component is locked and ignores any control sequences from the attached component until the attached component is powered back on and the attached component sends a correct unlock sequence to the control interface to unlock the powered component.

Locking system to protect a powered component interface from erroneous

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Orefield, PA, United States of America

James T Clee