Tandem Computers Incorporated

Compaq Computer Corporation, Inc.

James Stevens Klecka

William J Watson

John C Krause

David P Sonnier

William F Bruckert

Richard W Cutts, Jr

Linda Ellen Zalzala

Robert W Horst

David J Garcia

William P Bunton

Robert L Jardine

John Michael Brown

John D Coddington

Douglas E Jewett

William Edward Baker

Susan S Meredith

Steven C Meyers

Geoffrey I Iswandhi

Stephen G Low

Daniel L Fowler

Nikhil A Mehta

Patricia L Whiteside

Frank A Williams

Randall G Banton

Paul N Hintikka

Richard Alan Vrba

Curtis Willard Jones, Jr

Gary F Campbell

Harry Frank Elrod

Wiliam P Bunton

Larry Leonard Lamano

Kyran Wilfred Fey, Jr

Barry Lee Drexler

A logical processor is formed from a pair of processor units operating in close synchrony to perform self-check operations. Outputs of one of the processor units are compared to that of the other processor unit. When one of the processor units experiences an error, creating a divergence, that error and/or divergence will be made known to the Master processor which will then determine if recovery from the error can be made and, if so, save its processing state to memory, cause a reset of both processor units to an initial state to begin executing reinitialization code using the prior saved state for both processor units.

Error self-checking and recovery using lock-step processor pair architecture

A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the local CPU clock. The CPUs are forced to take the same number of CPU clock cycles to complete the I/O operations. When the I/O operation is complete the internal processing of the instruction stream continues in a manner which is clock aligned in each of the multiple CPUs but which may be separate in real time due to oscillator drift. Accumulated drift is periodically removed by a timed interrupt which forces resynchronization of the CPUs in real time.

High-performance fault tolerant computer system with clock length

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Fail-fast, fail-functional, fault-tolerant multiprocessor system

Two identical streams of multi-bit symbols are received by a pair of storage elements, each having multiple locations and first and second pointer counters respectively identifying the locations at which received symbols are stored and from which stored symbols are retrieved. The storage elements are synchronized by providing each with a SYNC symbol that, when detected, causes the pointer counters to be placed in a predetermined (reset) state on one transition of a SYNC clock signal, releasing the pointer counters at the same time on a following transition of the SYNC clock signal.

Synchronized data transmission between elements of a processing system

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Lexington, TX, United States of America

James Stevens Klecka