Hewlett-packard Development Company, L.P.

Hewlett-packard Company

James Steven Wells

Samuel D Naffziger

Christian Laszlo Belady

Eric C Peterson

Shaun Lee Harris

Brent A Boudreaux

Gary Williams

Roy M Zeighami

Stuart C Haden

Paul Anthony Wirtzberger

Jeffrey Christenson

Michael C Day

Gerard M Blair

Jeffrey N Metcalf

Greg Huff

David A Klein

Eugene Z Berta

An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.

Multi-processor module

A system and method for actively deskewing synchronous clocks in a VLSI circuit by introducing a controllable delay unit within a local clock buffer within each of a number of circuit zones and applying a controllable delay at each of the local clock buffers in response to a phase comparison of clock signals from one or more adjacent clock zones. The system can be added to any of a number of various clock distribution networks on a VLSI circuit through the introduction of controllable clock zone buffers and localized phase comparators. By adjusting each localized clock buffer delay unit in response to measured clock signal phase differences from adjacent circuit zones, clock skew problems can be minimized across various clock zones on a VLSI circuit.

System and method for deskewing synchronous clocks in a very large scale integrated circuit

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Windsor, CO, United States of America

James Steven Wells