Intel Corporation

James Steven Burns

Stefan Rusu

Devadatta V Bodas

David J Ayers

Russell Jerome Fenger

Baskaran Ganesan

Suresh Sugumar

Sundaravarathan R Iyengar

Feranak Nelson

Krishnakanth Venkata Sistla

Ankush Varma

Vivek Garg

Vivek Tiwari

Martin Rowland

John M Powell, Jr

Edward Thomas Grochowski

Inder M Sodhi

Sailesh Kottapalli

Kenneth D Shoemaker

Bharadwaj Pudipeddi

Marsha Eng

Cesar A Quiroz

Mallik Bulusu

Robert Charles Swanson

James W Alexander

Ashish V Choubal

Ramamurthy Krithivas

Sudarshan Kumar

Palsamy Sakthikumar

Arvind Raman

Muralidhar Rajappa

Johan G Van De Groenendaal

Dheemanth Nagaraj

Russell J Wunderlich

Thi Dang

Jagannath Coimbatore Premkumar

Tom E Wang

Sudhir Muthyalapati

Since the maximum power consumption is largely a concern at the power supply domain, a limited number of nodes may be allowed to consume their maximum power consumption by preventing other nodes from consuming their maximum power consumption. This approach may be used either instead of or in cooperation with existing maximum power consumption regulators.

Controlling power consumption in processor-based systems and components thereof

A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.

Dynamic power limit sharing in a platform

In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.

Dynamically measuring power consumption in a processor

Methods, apparatuses, and systems may provide a sensor to monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM. A switch, connected to an output of the sensor, controls power to the non-volatile RAM, and a voltage regulator regulates a voltage of the non-volatile RAM and the volatile RAM. One or more memory slots receive the non-volatile RAM and the volatile RAM, and a processor receives information from the sensor, and controls the voltage regulator based on the received information. The voltage regulator comprises a plurality of registers to store power consumption information of the non-volatile RAM and the volatile RAM.

Power management in dual memory platforms

A method and system for dynamic or run-time reallocation of leakage current and dynamic power supply current of a processor. In one embodiment of the invention, the processor uses the variation in the leakage current of the processor to reduce the maximum current dissipation or power supply current of the processor (ICC). By reducing the maximum current dissipation, the system cost can be reduced as a less expensive power delivery system is required in one embodiment of the invention.

Method and system for run-time reallocation of leakage current and dynamic power supply current

Methods and apparatus are disclosed to improve system boot speed. A disclosed example method includes associating a first serial peripheral interface (SPI) with a baseboard management controller (BMC), copying an image from the first SPI to a volatile memory in response to receiving power at the BMC, and in response to receiving an access request associated with the first SPI, providing access to the image stored in the volatile memory.

System and apparatus to improve boot speed in serial peripheral interface system using a baseboard management controller

In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

Increasing power efficiency of turbo mode operation in a processor

Systems and methods of operating a computing system may involve identifying a plurality of state values, wherein each state value corresponds to a computing thread associated with a processor. An average value can be determined for the plurality of state values, wherein a determination may be made as to whether to grant a frequency boost request based at least in part on the average value.

Efficient frequency boost operation

A power control unit (PCU) may reduce the core wake-up latency in a computer system by concurrently waking-up the remaining cores after the first core is woken-up. The power control unit may detect arrival of a first, second, and a third interrupt directed at a first, second, and a third core. The power control unit may check whether the second interrupt occurs within a first period, wherein the first period is counted after waking-up of the first core is complete. The power control unit may then wake-up the second and the third core concurrently if the second interrupt occurs within the first period after the wake-up activity of the first core is complete. The first period may at least equal twice the time required for a first credit to be returned and next credit to be accepted.

Reducing core wake-up latency in a computer system

A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.

Method and apparatus to limit current-change induced voltage changes in a microcircuit

A method for adjusting the voltage and frequency to minimize power dissipation in a processor. The method of one embodiment comprises determining a power consumption value. The power consumption value is evaluated to obtain a new operating point. The new operating point is compared with a present operating point. A frequency setting and a voltage setting are adjusted to correspond to the new operating point if the new operating point is different from the present operating point.

Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system in response to compute load

Growing community of inventors

Cupertino, CA, United States of America

James Steven Burns