International Business Machines Corporation

Semtech Corporation

James Stephen Mason

Hayden C Cranford, Jr

Louis Lu-Chen Hsu

Chih-Chao Yang

Louis L Hsu

Michael Anthony Sorna

Gareth John Nicholls

Thomas J Bardsley

Philip J Murfet

Louis C Hsu

Oleg Gluschenkov

Karl David Selander

Huihao Xu

Matthew B Baecher

Matthew R Cordrey-Gale

Phil J Murfet

Jack Allan Mandelman

Brian L Ji

Jeremy K Stephens

Steven John Zier

Charlie Chornglii Hwang

Mark R Taylor

Jonah Edward Nuttgens

Joseph O Marsh

Andrew Hana

Westerfield John Ficken

Richard W Oldrey

Samuel Taylor Ray

David W Kruger

Michael A Soma

Gareth J Nickolls

Matt R Cordrey-Gale

A photodiode current comparison circuit has a first current source coupled to a circuit node configurable to operate in a first mode, a second current source coupled to the circuit node configurable to operate in a second mode opposite the first mode, and a third current source switchable to route a current to the circuit node in response to a data signal using a transistor coupled between the circuit node and the third current source. A photodiode is coupled to the circuit node. In a first configuration, an anode of the photodiode is coupled to the circuit node and a cathode of the photodiode is coupled to a power supply terminal. In a second configuration, a cathode of the photodiode is coupled to the circuit node and an anode of the photodiode is coupled to a power supply terminal. An amplifier provides an error signal of the photodiode.

Configurable laser monitor photodiode in optical modulation amplitude controller

An OMA controller circuit utilizes a first ADC with an input coupled for receiving a residual error signal indicating a difference between a monitoring signal and a target data signal. A second ADC has an input coupled for receiving the target data signal. A first digital filter has an input coupled to an output of the first ADC, and a second digital filter has an input coupled to an output of the second ADC. A digital multiplier has a first input coupled to an output of the first digital filter and a second input coupled to an output of the second digital filter. An integrator has an input coupled to an output of the digital multiplier and an output providing an average error signal with sign and magnitude. The digital multiplier uses a four quadrant multiplier to perform a cross-correlation on the residual error and the target data signal.

Digital implementation of closed loop optical modulation amplitude controller for laser diode

An apparatus and method for providing standby power to a node of a distributed system of devices. The apparatus includes: a current manager operable to manage supply of current to a device at the node; a normal current supplier operable to supply normal operating current to the device; and a super capacitor at the node operable to supply standby operating current to the device under control of the current manager when the normal current supplier fails to supply the normal operating current to the device. The apparatus preferably further comprises a switching regulator, operable in electrical communication with the super capacitor and the device, to regulate the standby operating current to the device.

Apparatus and method for distributed standby power provision

A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.

Implementing tamper resistant integrated circuit chips

A receiver for a data communications system comprises: a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.

Data communications systems

A machine-readable medium thereupon stored a design structure; the design structure includes a receiver for a data communications system. The receiver includes a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.

Structure for data communications systems

A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages () connected in parallel with each amplifier stage having a gain control means. Input signal means () are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage () are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (). The gain of the amplifier array has a range from a low gain setting with a first amplifier stage () enabled, through increasing gain settings as the gain of the first amplifier stage is increased from a minimum to a maximum gain, a second amplifier stage () can then be enabled in addition to the first amplifier stage and the gain of the second amplifier stage increased from a minimum to a maximum gain, further amplifier stages are enabled as available up to a maximum gain setting for the amplifier array. Each amplifier stage that is enabled has a decreasingly attenuated input signal and a final amplifier stage to be enabled has a full input signal ().

Variable gain amplifier

A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined.

Structure for on-chip electromigration monitoring system

An apparatus is provided for implementing an enhanced hand shake protocol for microelectronic communication systems. A transmitter and a receiver is coupled together by a transmission link. The transmitter receives an idle input. The idle input is activated when the transmitter is not transmitting data and the transmitter applies a first commonmode level to the receiving unit. The idle input is deactivated when the transmitter is ready to transmit data and the transmitter raises the common mode level to the receiving unit. Responsive to the receiver detecting the common mode level up-movement, then the receiver receives the transmitted data signals. After the desired data has been sent, thetransmitter terminates communications, drops the common mode level with the idle input being activated.

Apparatus for implementing enhanced hand shake protocol in microelectronic communication systems

A method is provided for monitoring interconnect resistance within a semiconductor chip assembly, A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition.

On-chip electromigration monitoring

A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the information to the transmitter. The receiver is further operable to perform adaptive equalization to receive the signal transmitted by the transmitter.

High-speed multi-mode receiver

Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal. The testing includes skewing a differential output termination impedance, adjusting a differential receiver circuit voltage offset, selecting a differential driver circuit power level, enabling a decoder which activates only one differential driver circuit segment per test sequence, activating a segment, stimulating the differential driver circuit with digital test patterns, receiving differential driver circuit output, converting the output to a single-ended signal, and observing the single-ended signal.

System and method of digitally testing an analog driver circuit

A structure and method for power distribution to a network for an integrated circuit chip complex are provided. The chip complex has at least two sectors, each having at least one power providing connection with at least one of said connections beings individually addressable by, and isolatable from, a given power source. At least one MEMS is positioned to selectively connect and disconnect said at least one connection to and from said given power source.

Power network reconfiguration using MEM switches

A data receiver is provided which includes a front end interface circuit having an alternating current (AC) transmission receiving mode and a direct current (DC) transmission receiving mode. The front end interface circuit includes an offset compensation circuit operable to compensate a DC voltage offset between a pair of differential signals input to the data receiver. The front end interface circuit further includes an AC/DC selection unit operable to switch between (a) the DC transmission receiving mode, and (b) the AC transmission receiving mode, such that the data receiver is operable in (i) the DC transmission mode in which the offset compensation circuit is disabled, (ii) the DC transmission mode in which the offset compensation circuit is enabled, (iii) the AC transmission mode in which the offset compensation circuit is disabled, and (iv) the AC transmission receiving mode in which the offset compensation circuit is enabled.

Front end interface for data receiver

Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.

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Eastleigh, United Kingdom

James Stephen Mason