International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

James Stephen Fields, Jr

Guy L Guthrie

Ravi Kumar Arimilli

William John Starke

John Steven Dodson

Lakshminarayana Baba Arimilli

Leo James Clark

Sanjeev Ghai

Jeffrey A Stuecheli

Jody B Joyner

Derek E Williams

Praveen S Reddy

Benjiman L Goodman

Kevin Franklin Reick

Paul Frank Lecocq

Scott Barnett Swaney

George William Daly, Jr

Jerry Don Lewis

Warren Edward Maule

Edgar Rolando Cordero

Eric Eugene Retter

Kevin Charles Gower

Andrew Dale Walls

Michael Stephen Floyd

Thomas Pflueger

Timothy Michael Skergan

Bradley David McCredie

Brian Chan Monwai

Kenneth Lee Wright

Phillip G Williams

Jason Frederick Cantin

Steven R Kunkel

Andreas Bieswanger

Donald G Grice

Larry Scott Leitner

Appoloniel N Tankeh

Michael T Benhase

David Brian Glasco

Frank David Ferraiolo

Naresh Nayar

Bruce Gerard Mealey

John Michael Borkenhagen

Wolfgang Roesner

Eugen Schenfeld

Gary Dale Carpenter

Pak-kin Mak

Richard Loise Arndt

Lee Evan Eisen

Robert Alan Cargnoni

Mark Edward Dean

Alongkorn Kitamorn

David Otto Lewis

Andrew J Geissler

Mark Andrew Brittain

Michael John Mayfield

Norman Karl James

John Thomas Hollaway, Jr

Michael Youhour Lim

Kirk Samuel Livingston

Herwig Gustav Elfering

Yoanna Baumgartner

Paul Umbarger

Alan Hlava

Wayne L Lemmon

Anna Elman

Jeffery L Swarts

Kenneth Alan Riek

Denis A Smetana

Thomas J Heller

Michael Stephen Floys

Thomas K Heller, Jr

A mechanism is provided for buffer linking in a buffered solid state drive controller. Responsive to the buffered flash memory module receiving from a memory bus of a processor a memory command specifying a write operation, the mechanism initializes a first memory buffer in the buffered flash memory module. The mechanism associates the first memory buffer with an address of the write operation. The mechanism performs a compare operation to compare a previous and a next address with respect, to an address associated with the first memory buffer with a plurality of buffers. The mechanism assigns a link tag to at least one buffer identified in the compare operation and the first memory buffer to form a linked buffer set. The mechanism writes to the first memory buffer based on the memory command. The mechanism builds at least one input/output command to persist contents of the linked buffer set and writes the contents of the linked buffer set to at least one solid state drive according to the at least one input/output command.

Buffered automated flash controller connected directly to processor memory bus

A mechanism is provided for buffer linking in a buffered solid state drive controller. Responsive to the buffered flash memory module receiving from a memory bus of a processor a memory command specifying a write operation, the mechanism initializes a first memory buffer in the buffered flash memory module. The mechanism associates the first memory buffer with an address of the write operation. The mechanism performs a compare operation to compare a previous and a next address with respect to an address associated with the first memory buffer with a plurality of buffers. The mechanism assigns a link tag to at least one buffer identified in the compare operation and the first memory buffer to form a linked buffer set. The mechanism writes to the first memory buffer based on the memory command. The mechanism builds at least one input/output command to persist contents of the linked buffer set and writes the contents of the linked buffer set to at least one solid state drive according to the at least one input/output command.

A mechanism is provided for direct memory access in a storage device. Responsive to the buffered flash memory module receiving from a memory bus of a processor a memory command specifying a write operation, the mechanism initializes a first memory buffer in the buffered flash memory module. The mechanism writes to the first memory buffer based on the memory command. Responsive to the buffer being full, the mechanism deterministically maps addresses from the first memory buffer to a plurality of solid state drives in the buffered flash memory module using a modular mask based on a stripe size. The mechanism builds a plurality of input/output commands to persist contents of the first memory buffer to the plurality of solid state drives according to the deterministic mapping and writes the contents of the first memory buffer to the plurality of solid state drives in the buffered flash memory module according to the plurality of input/output commands.

Symmetric multi-processor (SMP) nodes are dynamically configured via SMP sockets that use SMP optically-connected switches to dynamically connect SMP optically-connected links connected to the SMP nodes to form SMP domains based on best matched expected workloads for coherent traffic for exchanging SMP coherent information. The SMP nodes are dynamically added to one of the SMP domains and/or dynamically removed from one of the SMP domains.

Dynamic formation of symmetric multi-processor (SMP) domains

A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing

In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

Apparatus for operating cache-inhibited memory mapped commands to access registers

In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.

Data processing system and method for efficient coherency communication utilizing coherency domain indicators

In a cache coherent data processing system including at least first and second coherency domains, a master performs a first broadcast of an operation within the cache coherent data processing system that is limited in scope of transmission to the first coherency domain. The master receives a response of the first coherency domain to the first broadcast of the operation. If the response indicates the operation cannot be serviced in the first coherency domain alone, the master increases the scope of transmission by performing a second broadcast of the operation in both the first and second coherency domains. If the response indicates the operation can be serviced in the first coherency domain, the master refrains from performing the second broadcast.

Data processing system and method for efficient coherency communication utilizing coherency domains

In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Latencies of requests and combined responses between the plurality of agents are observed. Each of the plurality of agents is configured with a respective duration of a protection window extension by reference to the observed latencies. Each protection window extension is a period following receipt of a combined response during winch an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. The plurality of agents employing protection window extensions in accordance with the configuration, and at least two of the agents have protection window extensions of differing durations.

Protecting ownership transfer with non-uniform protection windows

A method and apparatus for performing data prefetch in a multiprocessor system are disclosed. The multiprocessor system includes multiple processors, each having a cache memory. The cache memory is subdivided into multiple slices. A group of prefetch requests is initially issued by a requesting processor in the multiprocessor system. Each prefetch request is intended for one of the respective slices of the cache memory of the requesting processor. In response to the prefetch requests being missed in the cache memory of the requesting processor, the prefetch requests are merged into one combined prefetch request. The combined prefetch request is then sent to the cache memories of all the non-requesting processors within the multiprocessor system. In response to a combined clean response from the cache memories of all the non-requesting processors, data are then obtained for the combined prefetch request from a system memory.

Method and apparatus for performing data prefetch in a multiprocessor system

A cache coherent data processing system includes at least first and second coherency domains coupled for communication. The first and second coherency domains each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains based, at least in part, upon a type of the operation. The master then performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.

Data processing system and method for predictively selecting a scope of broadcast of an operation

A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.

Ticket-based operation tracking

Illustrative embodiments disclose a data processing system providing low-level hardware access to in-band and out-of-band firmware. The data processing system includes a plurality of chips that includes at least one processor chip and a plurality of support chips. At least one processor chip includes a field replaceable unit support interface master that uses a field replaceable unit support interface serial transmission protocol to communicate with the plurality of support chips. Each one of the plurality of support chips includes a field replaceable unit support interface slave in, with ones of the plurality of chips that include a processor also include the field replaceable unit support interface master, and ones of the plurality of chips that do not include the processor include only the field replaceable unit support interface slave. Only the field replaceable unit support interface master possesses conversion logic.

Providing low-level hardware access to in-band and out-of-band firmware

A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

L2 cache controller with slice directory and unified cache structure

Growing community of inventors

Austin, TX, United States of America

James Stephen Fields, Jr