Micron Technology Incorporated

Lodestar Licensing Group LLC

James S Rehmeyer

George B Raad

Timothy B Cowles

Debra M Bell

Christopher Gordon Wieduwilt

Jonathan Scott Parry

Anthony D Veches

Joshua E Alzheimer

Nathaniel J Meier

Seth A Eichmeyer

Dale Herber Hiscock

Michael Kaminski

Libo Wang

Di Wu

Eric J Stave

Jason M Johnson

Joo-Sang Lee

Miles S Wiscombe

Gary L Howe

Lawrence D Smith

Dean D Gans

David R Brown

Yoshinori Fujiwara

Brian P Callaway

Markus H Geiger

Benjamin Johnson

Robert Bunnell

Stephen Michael Kaminski

Timothy Mowry Hollis

John Frederic Schreck

Kenji Yoshida

Brian W Huber

Baekkyu Choi

Brett Kenneth Dodds

Yogesh Sharma

Sang-Kyun Park

Toshihiko Miyashita

Dale H Hiscock

Makoto Kitayama

Christopher D Wieduwilt

Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands. A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

Apparatus with refresh management mechanism

Systems are disclosed. A system may include a host device, a first memory device, and a second memory device. Each of the first memory device and the second memory device are configured to be refreshed substantially simultaneously responsive to a receipt of a refresh command from the host device. A count value of a refresh address counter of the first memory device is different than a count value of a refresh address counter of the second memory device. Associated methods are also described.

Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems

Fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. Fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. The fuse arrays can be fabricated and then programmed to cause different delays for different dies.

Fuse delay of a command in a memory package

An antifuse device, including a gate having a gate dielectric layer; a first doping region connected to a first end of the gate; a second doping region connected to a second end of the gate, the second end being opposite to the first end of the gate; a channel that is disposed under the gate and that connects the first doping region and the second doping region; and an interconnection jumper that electrically connects the first doping region and the second doping region.

Antifuse device having interconnect jumper

An improved memory module and methods for constructing the same are disclosed herein. The memory module includes a substrate having a first surface and a second surface opposite the first surface, each having a central portion, a first array area and a second array area. The first array area is cooler than the second array area during operation. The memory module also includes a power management integrated circuit attached to the central portion of the first surface. The memory module also includes a first semiconductor die attached to the substrate in the first array area. The first semiconductor die has a first performance rating of an operating parameter at high temperatures. The memory module also includes a second semiconductor die attached to the substrate in the second array area. The second semiconductor die has a second performance rating of an operating parameter better than the first performance rating at high temperatures.

Management of heat on a semiconductor device and methods for producing the same

Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device.

Memory with per die temperature-compensated refresh control

Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

Memory with partial array refresh

Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Methods for independent memory bank maintenance and memory devices and systems employing the same

Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

Apparatus with data-rate-based voltage control mechanism and methods for operating the same

Methods, systems, and devices for power management for a memory device are described. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range, and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit (PMIC) that is coupled with the one or more memory dies and provides the supply voltages to the one or more memory dies. The PMIC may be configured to provide, to the one or more memory dies, a first voltage that is within the first defined voltage range as the first supply voltage and a second voltage that is outside the second defined voltage range as the second supply voltage.

Power management for a memory device

Signaling indicative of a command to initialize a plurality of memory dies of a memory device can be received by the memory device. Initialization of a memory die of the memory device can be delayed, at the memory die and based at least in part on fuse states of an array of fuses of the memory die, by an amount of time relative to receipt of the signaling by the memory device. Delaying initialization of memory dies of the memory device in a staggered or asynchronous manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.

Delay of initialization at memory die

Apparatuses and methods can be related to placing memory in a computing system. The memory modules can be placed in memory slots to couple the memory modules to the computing system. The memory modules and/or the memory slots can have thermal qualities which can be utilized to determine which of the memory modules are placed on which of the memory slots.

Memory placement in a computing system

A timing of an execution of a command in a memory device can be affected delay elements. The delay elements of a unit of delay elements can cause variable delays of the command paths. The delay elements can be activated based on settings stored in a fuse array of a memory device. The delay elements can be used to change a timing of current draw of the memory devices.

Delay elements for command timing in a memory device

A memory device includes a memory cell array and a set of fuse banks including a common fuse bank storing common bit information corresponding to a plurality of defective memory cells in the memory cell array. The memory device including a plurality of match sub-circuits corresponding to respective defective memory cells of the plurality of defective memory cells. Each match sub-circuit can be configured to provide a determination of whether a memory cell address of a memory cell of the memory cell array matches an address of the respective defective memory cell. The plurality of match sub-circuit can include a shared common bit-processing circuit that is configured to receive common bit-by-bit results of a comparison between a portion of the memory cell address and the common bit information. The common bit-processing circuit can determine whether the common bit information matches the portion of the memory cell address.

Shared components in fuse match logic

Growing community of inventors

Boise, ID, United States of America

James S Rehmeyer