Motorola Corporation

James S Irwin

Robert C Ledzius

Dhirajlal N Manvar

Robert E Stengel

Philip P Macnak

Robert S Kaltenecker

Ralph T Enderby

Wayne P Shepherd

David F Moeller

Walter L Davis

William J Ooms

Jose I Suarez

David S Peckham

Robert J Higgins, Jr

Francis Robert Steel

Merle L Gilmore

Karl J Huehne

A cross-coupled cascode voltage controlled oscillator including a variable-frequency tank circuit, first and second cascode-coupled active devices coupled to the tank circuit, and third and fourth cascode-coupled active devices coupled to the tank circuit, the first and second active devices being cross-coupled to the third and fourth active devices. The invention produces lower drain the gate voltages resulting in fewer device failures.

Cross coupled cascode voltage controlled oscillator

Given a target frequency (F.sub.VE), a reference frequency (F.sub.R), an error limit (E.sub.L), and a first divider range (150), a first (R) and a second (N) integer divider value are computed. First, an initial first divider (R) is selected (152). Then, a second divider (N) is computed as equal to the target frequency (F.sub.VE) divided by the reference frequency (F.sub.R) multiplied times the selected first divider (154). Then an error term (E) is computed to quantify the error introduced by using integers as dividers (156). The divider terms are accepted (166) if the error term is less than the error limit (158). Otherwise, a new first integer divider (R) is selected (160), repeating the computation of the second (N) divider (154), the computation of the error (E) term (156), and the test of the error term (E) against a limit as a loop (158). This loop is repeated until either the error term (E) is less than the error (E.sub.L) limit (158), or the selected first divider term (R) is outside its specified range (162).

Optimized computation of first and second divider values for a phase

A CMOS implemented output buffer (10) provides ECL level output signals. The output buffer (10) is implemented in two stages. The first stage (36) includes an inverter having a resistor (39) in series with a P-channel transistor (38) and an N-channel transistor (40) and provides the initial buffering. The resistor (39) in the first inverter stage (36) is used to reduce a cross-over current in the second drive stage (42). The second stage (42) provides additional drive capability and includes an integral level converter. The integral level converter is implemented as a P-channel transistor (44) connected in series with the P-channel and N-channel output driver transistors (53 and 55). The P-channel transistor (44) provides the level shifting function to ECL levels for the second stage. The bias level of the P-channel transistor (44) determines the output logic swing.

CMOS implemented output buffer circuit for providing ECL level signals

A phase locked loop (PLL) system receiving a reference frequency and generating an output frequency has a charge pump (28), loop filter (38), an N frequency divider (32), an R frequency divider (24), a Voltage Controlled Oscillator (30) and a phase detector (26). The charge pump (28) has a high current output (62) and a low current output (60). The loop filter (38) responsively coupled to the charge pump (28) has a first pole filter that includes a high current first pole filter capacitor (66), a high current first pole damping resistor (70), a low current first pole filter capacitor (64), a low current first pole damping resistor (68), and a first pole filter capacitor (72). A second pole filter can be added that includes a second pole filter capacitor (76), a second pole damping resistor (74), and a feed forward capacitor (78).

Adaptive phase locked loop system with charge pump having dual current

A method and apparatus for extracting digital information (111) from an asynchronous data stream (101) is achieved by providing a data stream (101) that is clocked at a data stream clock rate (210). A sampled data stream (103) is produced by sampling the asynchronous data stream at a first clock rate (105), which is independent of the data stream clock rate (210). Using the sampled data stream (103), a recovered clock (107) is generated. The recovered clock (107) is then used to extract the digital information (111) from the sampled data stream (103).

Method and apparatus for extracting digital information from an

A sigma-delta modulator (50, 100) attenuates a frequency domain characteristic of a feedback signal to a first stage (60) of the modulator (50, 100) near f.sub.s /2, where f.sub.s is the modulator's (50, 100) clock frequency. The modulator (50, 100) thus virtually eliminates in-band tones which are characteristic of known sigma-delta modulators, without complex dithering schemes. In one embodiment, the sigma-delta modulator (50, 100) includes a two-tap finite impulse response (FIR) filter (80) within a feedback loop of the modulator (50, 100). The two-tap FIR filter (80) smoothes transitions at an output of a second stage (70) to provide the feedback signal to the first stage (60). This architecture is useful for either a digital-to-analog sigma-delta modulator (50) or an analog-to-digital sigma-delta modulator (100).

Sigma-delta modulator with improved tone rejection and method therefor

A flexible data interface (21, 22) for a digital-to-analog converter (25, 26) includes a mute circuit (46, 70, 71 ) to mute and de-mute input data in 6 dB steps over a time period such as one-quarter of a second. The mute circuit includes a counter (46) to provide mute signals, a decoder (70) to decode the mute signals, and a shift matrix (71) to shift the data from zero to the maximum number of bits in response to the decoded signals. The interface (21, 22) includes a programmable shift register (43) to allow different data word lengths, such as 20-, 18-, or 16-bit, to be presented to the digital-to-analog converter (25, 26). The interface (21, 22) also includes a multiplexer (47) to allow left- and right-channel data to be received either time-multiplexed on a single pin, or on two separate pins.

Digital-to-analog converter with a flexible data interface

A phase locked loop (20) includes a standby control circuit (30) and recovers from standby with minimum lock time. A reference counter (21), a loop counter portion (22, 23) and a phase detector (24) are disabled in response to an activation of a standby signal. Both the reference counter (21) and the loop counter portion (22, 23) are enabled in response to a deactivation of the standby signal. A voltage controlled oscillator (VCO) (26) output signal is decoupled from an input of the loop counter portion (22, 23) in response to an activation of a loop counter output signal. The VCO output signal is next recoupled to the input of the loop counter portion (22, 23) in response to an activation of a reference counter output signal. Finally, the phase detector (24) is enabled. In one embodiment, the loop counter portion (22, 23) includes a prescaler (22) which does not have a separate reset input, and a separate loop counter (23).

Method and apparatus for standby recovery in a phase locked loop

A sigma-delta digital-to-analog converter (DAC) (40) receives oversampled input data representative of an analog signal. The data may be optionally interpolated to a higher rate in a interpolator (41). A noise-shaping sigma-delta modulator (42) is connected to the output of the interpolator (41). The output of the modulator (42) is provided to a finite impulse response (FIR) filter (43). The FIR filter (43) has a frequency response characteristic which reduces the shaped noise and aliased components. This noise has a tendency to intermodulate back into the DAC's passband. The FIR filter (43) uses a series of flip-flops (81, 82, 83) functioning as delay elements with well-controlled timing edges. The outputs of the flip-flops (81, 82, 83) control current sources (91, 92, 93) weighted according to corresponding filter coefficients. The outputs of the current sources (91, 92, 93) are then summed in a summing device such as an amplifier (101).

Sigma-delta digital-to-analog converter with reduced noise

A sigma-delta digital-to-analog converter (20) reduces even order distortion, such as a DC offset, in an output signal by chopping the output signal alternately with set and reset pulses. The sigma-delta digital-to-analog converter (20) includes a sigma-delta modulator (25), a chop circuit (261) associated with a corresponding bit of the sigma-delta modulator (25), and an output buffer (264) for providing the output signal. The chop circuit (261) alternately inserts first and second logic levels into an output data stream of the sigma-delta modulator (25) before providing it to the output buffer (264). Even-order distortion is eliminated with only a tolerable attenuation of the output signal.

Sigma-delta digital-to-analog converter with reduced distortion

A digital-to-analog converter (20) with improved performance includes an offset/scaler (23), a sigma-delta modulator (25), and an analog summing network (26). In one embodiment, the offset/scaler (23) scales an input signal by a predetermined amount, such as three-quarters, to compensate for nonlinearities in a transfer characteristic of the sigma-delta modulator (25). In another embodiment, the sigma-delta modulator (25) is a sufficiently-resolved sigma-delta modulator. The offset/scaler (23) provides an offset to the sufficiently-resolved sigma-delta modulator (25) sufficient to force a coarse bit thereof into an idle pattern.

Digital-to-analog converter with improved performance and method therefor

A digital signal having a plurality of bits is apportioned by the DAC into a plurality of words, at least one of which has a plurality of bits. Each of the plurality of words is then processed in an energy signal producing means, such as a .SIGMA.-.DELTA. modulator, to produce an output energy signal whose time average represents the input digital word portion. The energy output signals are then summed to provide the analog signal.

Multi-modulator digital-to-analog converter

The charge pump circuit of a phase locked loop has a sensing device, latch and charge pump. When there are contemporaneous up and down signals being produced by the charge pump, a reset signal is provided from the sensing device to a latch which is coupled between the input to the circuit and the pump. Input signals are then inhibited from reaching the charge pump.

Phase locked loop having a charge pump with reset

A digital signal having a plurality of bits is received by a converter. Two of the bits, the most significant bit and a second bit which is not the most significant bit or the second most significant bit, are tapped from the output and used as a feedback signal. These two bits are also used to form an analog output signal. The two bits are attenuated using a weighted network and then summed to provide the analog output signal.

.SIGMA.-.DELTA.modulator for digital-to-analog converter

An analog signal is input to a converter where a feedback signal is subtracted to form an analog error signal. The analog error signal is then processed through a first quantizer to provide a course output bit. The difference between the input and output of the first quantizer is then processed through a second quantizer to provide a trim output bit. The two bits are combined and returned as the feedback signal and are provided to a decimation filter which will provide the digital output representation of the analog input.

Growing community of inventors

Paige, TX, United States of America

James S Irwin