Hewlett-Packard Company

James S Ignowski

Charles E Moore

Travis N Blalock

Rajeev Badyal

Richard A Baumgartner

Larry S Metz

Ran-Fun Chiu

Sui-hing Leung

Thomas M Walley

Li Ching Tsai

Richard A Baugh

Ralph E Lovelace

Stuart A Bell

Robert A Zimmer

Hugh S Wallace

Kenneth R Stafford

David J Gampell

An analog, fully integrated, partial response maximum likelihood (PRML) read channel utilizing a high-performance analog delay line, an analog adaptive equalizer and an analog Viterbi detector is provided, resulting in saved space, performance gains, and lower power consumption. For signal detection and reconstruction used in read operations, the partial response maximum likelihood (PRML) read channel includes a variable gain amplifier coupled to a lowpass filter for input to an adaptive analog equalizer. The adaptive analog equalizer comprises an analog delay line and an analog feedforward equalizer (FFE). An analog Viterbi detector employs maximum-likelihood sequence estimation (MLSE) techniques to performs the signal detection function. A decoder/descrambler produces a final reconstructed signal. The analog implementation of a partial response maximum likelihood (PRML) read channel also includes a scrambler/encoder coupled to a write precompensation circuit for output to a separate write head.

Analog implementation of a partial response maximum likelihood (PRML)

A video DAC for driving video displays with reduced power dissipation is presented. This is accomplished using a dual driver circuit connected to a current mirror, the dual driver comprising a strong driver and a weak driver. The dual driver permits switching current between the video load and a dummy load. The current to the dummy load is disabled during periods when the video signal remains steady for a predetermined period of time. The dual driver, using the weak driver, disables the current to the dummy load during video blanking and synchronization periods. This scheme substantially reduces the power dissipation in the DAC.

Power reduction technique for current mode digital-to-analog converters

An optical transmitter/receiver pair has an integrated CMOS circuit that provides a current flow to a pre-biased solid state light emitting device (LED) in response to the presence or absence of a digital input signal. The current flow is augmented at the rising and falling edges of the input signal to enhance turn-on and turn-off speed of the LED. The LED is optically coupled to a photodiode that produces a current flow in response to illumination. The photodiode is shielded from spurious electronic noise by a transparent shield and the output of the photodiode is amplified to produce an output voltage, which is connected to a capacitively delayed voltage divider. The voltage divider generates a time delayed threshold voltage connectable along with the output voltage to the inputs of a comparator.

Circuits for realizing an optical isolator

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Santa Clara, CA, United States of America

James S Ignowski